Patents by Inventor Tomohiro Iguchi
Tomohiro Iguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250385581Abstract: A rotor, which is applicable to a wound-field rotating electric machine, includes: a rotor core having main pole portions provided respectively for magnetic poles aligned in a circumferential direction, each of the main pole portions protruding in a radial direction; and a field coil wound on the main pole portions of the rotor core. Moreover, the field coil has a coil end part located axially outside the rotor core. An annular member is provided, on a radially outer side of the coil end part, in such a manner as to surround the coil end part.Type: ApplicationFiled: August 18, 2025Publication date: December 18, 2025Inventors: Yoshimasa KANEDA, Masahiro SEGUCHI, Tomohiro IGUCHI, Hiroyuki TSUCHIYA
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Publication number: 20250385580Abstract: A rotating electric machine includes a stator having a stator coil and a rotor having a rotor core and a field coil. The rotating electric machine is configured to have harmonic current flowing through the stator coil to induce field current in the field coil. The rotor further has a circuit module provided around a rotating shaft and connected with the field coil to form a resonant circuit together with the field coil, and a coil end cover covering a coil end part of the field coil which is located axially outside the rotor core. Moreover, the coil end cover is a balance adjustment member that adjusts weight balance of the rotor in the circumferential direction; and at least part of the coil end cover in the circumferential direction constitutes an adjustment portion where weight of the coil end cover has been reduced or increased.Type: ApplicationFiled: August 18, 2025Publication date: December 18, 2025Inventors: Yoshimasa KANEDA, Masahiro SEGUCHI, Tomohiro IGUCHI, Hiroyuki TSUCHIYA
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Patent number: 12355015Abstract: A semiconductor device includes first, second, and third metal layers on a surface of the insulating substrate. A first terminal is connected to the first metal layer at a first region. A second terminal is connected to the second metal layer at a second region. An output terminal is connected to the third metal layer. First chips are aligned along a first direction on the first metal layer. Second chips are aligned along the first direction on the third metal layer. A first wire connects a first upper electrode of a first chip to the third metal layer. A second wire connects a second upper electrode of a second chip to the second metal layer. The second chips are between the first chips and the third metal layer in a second direction perpendicular to the first direction. Available conductive routes between the first and second terminals are made more uniform.Type: GrantFiled: February 25, 2022Date of Patent: July 8, 2025Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Tomohiro Iguchi, Makoto Mizukami
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Patent number: 12165965Abstract: A semiconductor device according to an embodiment includes: an insulating substrate having a first metal layer and a second metal layer on a surface of the insulating substrate; a semiconductor chip including an upper electrode and a lower electrode, the upper electrode being electrically connected to the first metal layer, the lower electrode being electrically connected to the second metal layer; a first main terminal including a first end and a second end, the first end being electrically connected to the first metal layer; a second main terminal including a third end and a fourth end, the third end being electrically connected to the second metal layer; a first detection terminal being electrically connected between the first end and the second end of the first main terminal; and a second detection terminal being electrically connected to the first metal layer.Type: GrantFiled: August 23, 2023Date of Patent: December 10, 2024Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Tomohiro Iguchi, Tatsuya Hirakawa
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Publication number: 20240355693Abstract: According to one embodiment, a semiconductor device includes a semiconductor element on a substrate. A first surface of the semiconductor element faces away from the substrate and a second surface faces the substrate. A first surface electrode is on the first surface of the semiconductor element. A bonding wire is connected to the first surface electrode at a bonding portion. A first sealing member covers the bonding portion. A second sealing member covers a portion of the first surface electrode outside the bonding portion. A third sealing member covers the first sealing member and the second sealing member.Type: ApplicationFiled: April 9, 2024Publication date: October 24, 2024Inventors: Shogo MINAMI, Tomohiro IGUCHI, Katsuya SATO, Keiichiro MATSUO
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Publication number: 20240312947Abstract: A semiconductor device according to an embodiment includes: an insulating substrate having a first metal layer and a second metal layer; a semiconductor chip on the first metal layer having an upper electrode and a lower electrode connected to the first metal layer; a bonding wire having a first end portion connected to the upper electrode and a second end portion connected to the second metal layer; a first resin layer covering the semiconductor chip and the bonding wire, the first resin layer containing a first resin; a second resin layer covering a bonding portion between the first end portion and the upper electrode containing a second resin having a Young's modulus higher than that of the first resin; a third resin layer on the first resin layer, the third resin layer containing a third resin having a moisture permeability lower than that of the first resin.Type: ApplicationFiled: August 3, 2023Publication date: September 19, 2024Inventors: Tomohiro IGUCHI, Tatsuya HIRAKAWA, Shogo MINAMI, Hiroyuki MATSUO, Izuru KOMATSU
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Patent number: 12080680Abstract: A semiconductor device according to an embodiment includes a semiconductor layer, a metal layer, and a bonding layer provided between the semiconductor layer and the metal layer, the bonding layer including a plurality of silver particles, and the bonding layer including a region containing gold existing between the plurality of silver particles.Type: GrantFiled: August 29, 2022Date of Patent: September 3, 2024Assignees: Kabushiki Kaisba Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Makoto Mizukami, Tatsuya Hirakawa, Tomohiro Iguchi
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Publication number: 20230395485Abstract: A semiconductor device according to an embodiment includes: an insulating substrate having a first metal layer and a second metal layer on a surface of the insulating substrate; a semiconductor chip including an upper electrode and a lower electrode, the upper electrode being electrically connected to the first metal layer, the lower electrode being electrically connected to the second metal layer; a first main terminal including a first end and a second end, the first end being electrically connected to the first metal layer; a second main terminal including a third end and a fourth end, the third end being electrically connected to the second metal layer; a first detection terminal being electrically connected between the first end and the second end of the first main terminal; and a second detection terminal being electrically connected to the first metal layer.Type: ApplicationFiled: August 23, 2023Publication date: December 7, 2023Inventors: Tomohiro IGUCHI, Tatsuya HIRAKAWA
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Patent number: 11776892Abstract: A semiconductor device according to an embodiment includes: an insulating substrate having a first metal layer and a second metal layer on a surface of the insulating substrate; a semiconductor chip including an upper electrode and a lower electrode, the upper electrode being electrically connected to the first metal layer, the lower electrode being electrically connected to the second metal layer; a first main terminal including a first end and a second end, the first end being electrically connected to the first metal layer; a second main terminal including a third end and a fourth end, the third end being electrically connected to the second metal layer; a first detection terminal being electrically connected between the first end and the second end of the first main terminal; and a second detection terminal being electrically connected to the first metal layer.Type: GrantFiled: August 24, 2020Date of Patent: October 3, 2023Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Tomohiro Iguchi, Tatsuya Hirakawa
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Publication number: 20230299038Abstract: A semiconductor device according to the embodiment includes: a frame body having a wall surface; an insulating substrate surrounded by the frame body, the insulating substrate having a first metal layer and a second metal layer on a surface, the second metal layer being located between the first metal layer and the wall surface; a semiconductor chip including an electrode and provided on the first metal layer; and a bonding wire having a first bond portion connected to the electrode, a second bond portion connected to the second metal layer, and an intermediate portion between the first bond portion and the second bond portion; wherein a second angle formed between a second direction in which the second bond portion extends and the wall surface is smaller than a first angle formed between a first direction in which the intermediate portion extends and the wall surface.Type: ApplicationFiled: August 18, 2022Publication date: September 21, 2023Inventor: Tomohiro IGUCHI
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Publication number: 20230092229Abstract: A semiconductor device includes first, second, and third metal layers on a surface of the insulating substrate. A first terminal is connected to the first metal layer at a first region. A second terminal is connected to the second metal layer at a second region. An output terminal is connected to the third metal layer. First chips are aligned along a first direction on the first metal layer. Second chips are aligned along the first direction on the third metal layer. A first wire connects a first upper electrode of a first chip to the third metal layer. A second wire connects a second upper electrode of a second chip to the second metal layer. The second chips are between the first chips and the third metal layer in a second direction perpendicular to the first direction. Available conductive routes between the first and second terminals are made more uniform.Type: ApplicationFiled: February 25, 2022Publication date: March 23, 2023Inventors: Tomohiro IGUCHI, Makoto MIZUKAMI
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Publication number: 20230078259Abstract: A semiconductor device includes a semiconductor part, first and second electrodes, and first and second protective films. The first electrode is provided on the semiconductor part. The first protective film is provided on the semiconductor part and covers an outer edge of the first electrode. The second electrode is provided on the first electrode. The second electrode includes an outer edge partially covering the first protective film. The second protective film is provided on the semiconductor part and covers the first protective film and the outer edge of the second electrode.Type: ApplicationFiled: September 12, 2022Publication date: March 16, 2023Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yuchen HSU, Masayuki UCHIDA, Tomohiro IGUCHI
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Patent number: 11605613Abstract: According to an embodiment, provided is a semiconductor device includes an insulating substrate; a first main terminal; a second main terminal; an output terminal; a first metal layer connected to the first main terminal; a second metal layer connected to the second main terminal; a third metal layer disposed between the first metal layer and the second metal layer and connected to the output terminal; a first semiconductor chip and a second semiconductor chip provided on the first metal layer; and a third semiconductor chip and a fourth semiconductor chip provided on the third metal layer. The second metal layer includes a first slit. Alternatively, the third metal layer includes a second slit.Type: GrantFiled: March 11, 2021Date of Patent: March 14, 2023Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventor: Tomohiro Iguchi
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Publication number: 20220415848Abstract: A semiconductor device according to an embodiment includes a semiconductor layer, a metal layer, and a bonding layer provided between the semiconductor layer and the metal layer, the bonding layer including a plurality of silver particles, and the bonding layer including a region containing gold existing between the plurality of silver particles.Type: ApplicationFiled: August 29, 2022Publication date: December 29, 2022Inventors: Makoto MIZUKAMI, Tatsuya HIRAKAWA, Tomohiro IGUCHI
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Patent number: 11462508Abstract: A semiconductor device according to an embodiment includes a semiconductor layer, a metal layer, and a bonding layer provided between the semiconductor layer and the metal layer, the bonding layer including a plurality of silver particles, and the bonding layer including a region containing gold existing between the plurality of silver particles.Type: GrantFiled: August 31, 2020Date of Patent: October 4, 2022Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Makoto Mizukami, Tatsuya Hirakawa, Tomohiro Iguchi
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Publication number: 20210351161Abstract: According to an embodiment, provided is a semiconductor device includes an insulating substrate; a first main terminal; a second main terminal; an output terminal; a first metal layer connected to the first main terminal; a second metal layer connected to the second main terminal; a third metal layer disposed between the first metal layer and the second metal layer and connected to the output terminal; a first semiconductor chip and a second semiconductor chip provided on the first metal layer; and a third semiconductor chip and a fourth semiconductor chip provided on the third metal layer. The second metal layer includes a first slit. Alternatively, the third metal layer includes a second slit.Type: ApplicationFiled: March 11, 2021Publication date: November 11, 2021Inventor: Tomohiro Iguchi
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Publication number: 20210305204Abstract: A semiconductor device according to an embodiment includes a semiconductor layer, a metal layer, and a bonding layer provided between the semiconductor layer and the metal layer, the bonding layer including a plurality of silver particles, and the bonding layer including a region containing gold existing between the plurality of silver particles.Type: ApplicationFiled: August 31, 2020Publication date: September 30, 2021Inventors: Makoto MIZUKAMI, Tatsuya HIRAKAWA, Tomohiro IGUCHI
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Publication number: 20210305147Abstract: A semiconductor device according to an embodiment includes: an insulating substrate having a first metal layer and a second metal layer on a surface of the insulating substrate; a semiconductor chip including an upper electrode and a lower electrode, the upper electrode being electrically connected to the first metal layer, the lower electrode being electrically connected to the second metal layer; a first main terminal including a first end and a second end, the first end being electrically connected to the first metal layer; a second main terminal including a third end and a fourth end, the third end being electrically connected to the second metal layer; a first detection terminal being electrically connected between the first end and the second end of the first main terminal; and a second detection terminal being electrically connected to the first metal layer.Type: ApplicationFiled: August 24, 2020Publication date: September 30, 2021Inventors: Tomohiro IGUCHI, Tatsuya HIRAKAWA
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Patent number: 11098703Abstract: Provided is a variable displacement compressor capable of preventing intrusion of foreign matter into a second control valve. A variable displacement compressor 100 is equipped with a first control valve 300 controlling the opening degree of a supply passage 145, a check valve 350, a second control valve 400 controlling the opening degree of a discharge passage 146, and a back-pressure relief passage 147. The second control valve 400 has a back-pressure chamber 410 communicating with an intermediate supply passage 145b1, a valve chamber 420 in which a valve hole 103d and a discharge hole 431a are open and which constitutes a part of the discharge passage 146, a dividing member 430 dividing the back-pressure chamber 410 and the valve chamber 420 from each other, and a spool 440.Type: GrantFiled: February 9, 2018Date of Patent: August 24, 2021Assignee: Sanden Automotive Components CorporationInventors: Yukihiko Taguchi, Takashi Toida, Satoshi Terauchi, Tomohiro Iguchi, Yoshie Matsuzaki
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Patent number: 11081412Abstract: A semiconductor device of embodiments includes a first semiconductor chip; a metal plate having a first plane and a second plane facing the first plane and including a first ceramic plate provided between the first plane and the second plane; and a first insulating board provided between the first semiconductor chip and the metal plate and facing the first plane, in which the first ceramic plate does not exist between the first semiconductor chip and the second plane.Type: GrantFiled: February 20, 2020Date of Patent: August 3, 2021Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Takenori Yamada, Tomohiro Iguchi