Patents by Inventor Tomohiro Iguchi

Tomohiro Iguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240092285
    Abstract: A protector includes a case main body and a cover member. The cover member includes the cover main body part, the first cover part, and the second cover part. The first cover part and the second cover part are at the positions overlapping with each other in the longitudinal direction when viewed from the lateral direction of the cover main body part, and form an insertion space for passing a third extension part of a wiring material WH through in the lateral direction when viewed from the orthogonal direction of the cover main body part. The first cover part includes a movable part that is movable in the orthogonal direction with respect to the cover main body part when viewed from the lateral direction of the cover main body part, and a hinge part that rotatably connects the cover main body part and the movable part.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Shinji Kato, Kazuhiro Tsutida, Suginobu Iguchi, Takumasa Suzuki, Rikuya Saitou, Tomohiro Shibata
  • Publication number: 20230395485
    Abstract: A semiconductor device according to an embodiment includes: an insulating substrate having a first metal layer and a second metal layer on a surface of the insulating substrate; a semiconductor chip including an upper electrode and a lower electrode, the upper electrode being electrically connected to the first metal layer, the lower electrode being electrically connected to the second metal layer; a first main terminal including a first end and a second end, the first end being electrically connected to the first metal layer; a second main terminal including a third end and a fourth end, the third end being electrically connected to the second metal layer; a first detection terminal being electrically connected between the first end and the second end of the first main terminal; and a second detection terminal being electrically connected to the first metal layer.
    Type: Application
    Filed: August 23, 2023
    Publication date: December 7, 2023
    Inventors: Tomohiro IGUCHI, Tatsuya HIRAKAWA
  • Patent number: 11776892
    Abstract: A semiconductor device according to an embodiment includes: an insulating substrate having a first metal layer and a second metal layer on a surface of the insulating substrate; a semiconductor chip including an upper electrode and a lower electrode, the upper electrode being electrically connected to the first metal layer, the lower electrode being electrically connected to the second metal layer; a first main terminal including a first end and a second end, the first end being electrically connected to the first metal layer; a second main terminal including a third end and a fourth end, the third end being electrically connected to the second metal layer; a first detection terminal being electrically connected between the first end and the second end of the first main terminal; and a second detection terminal being electrically connected to the first metal layer.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: October 3, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tomohiro Iguchi, Tatsuya Hirakawa
  • Publication number: 20230299038
    Abstract: A semiconductor device according to the embodiment includes: a frame body having a wall surface; an insulating substrate surrounded by the frame body, the insulating substrate having a first metal layer and a second metal layer on a surface, the second metal layer being located between the first metal layer and the wall surface; a semiconductor chip including an electrode and provided on the first metal layer; and a bonding wire having a first bond portion connected to the electrode, a second bond portion connected to the second metal layer, and an intermediate portion between the first bond portion and the second bond portion; wherein a second angle formed between a second direction in which the second bond portion extends and the wall surface is smaller than a first angle formed between a first direction in which the intermediate portion extends and the wall surface.
    Type: Application
    Filed: August 18, 2022
    Publication date: September 21, 2023
    Inventor: Tomohiro IGUCHI
  • Publication number: 20230092229
    Abstract: A semiconductor device includes first, second, and third metal layers on a surface of the insulating substrate. A first terminal is connected to the first metal layer at a first region. A second terminal is connected to the second metal layer at a second region. An output terminal is connected to the third metal layer. First chips are aligned along a first direction on the first metal layer. Second chips are aligned along the first direction on the third metal layer. A first wire connects a first upper electrode of a first chip to the third metal layer. A second wire connects a second upper electrode of a second chip to the second metal layer. The second chips are between the first chips and the third metal layer in a second direction perpendicular to the first direction. Available conductive routes between the first and second terminals are made more uniform.
    Type: Application
    Filed: February 25, 2022
    Publication date: March 23, 2023
    Inventors: Tomohiro IGUCHI, Makoto MIZUKAMI
  • Publication number: 20230078259
    Abstract: A semiconductor device includes a semiconductor part, first and second electrodes, and first and second protective films. The first electrode is provided on the semiconductor part. The first protective film is provided on the semiconductor part and covers an outer edge of the first electrode. The second electrode is provided on the first electrode. The second electrode includes an outer edge partially covering the first protective film. The second protective film is provided on the semiconductor part and covers the first protective film and the outer edge of the second electrode.
    Type: Application
    Filed: September 12, 2022
    Publication date: March 16, 2023
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuchen HSU, Masayuki UCHIDA, Tomohiro IGUCHI
  • Patent number: 11605613
    Abstract: According to an embodiment, provided is a semiconductor device includes an insulating substrate; a first main terminal; a second main terminal; an output terminal; a first metal layer connected to the first main terminal; a second metal layer connected to the second main terminal; a third metal layer disposed between the first metal layer and the second metal layer and connected to the output terminal; a first semiconductor chip and a second semiconductor chip provided on the first metal layer; and a third semiconductor chip and a fourth semiconductor chip provided on the third metal layer. The second metal layer includes a first slit. Alternatively, the third metal layer includes a second slit.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: March 14, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Tomohiro Iguchi
  • Publication number: 20220415848
    Abstract: A semiconductor device according to an embodiment includes a semiconductor layer, a metal layer, and a bonding layer provided between the semiconductor layer and the metal layer, the bonding layer including a plurality of silver particles, and the bonding layer including a region containing gold existing between the plurality of silver particles.
    Type: Application
    Filed: August 29, 2022
    Publication date: December 29, 2022
    Inventors: Makoto MIZUKAMI, Tatsuya HIRAKAWA, Tomohiro IGUCHI
  • Patent number: 11462508
    Abstract: A semiconductor device according to an embodiment includes a semiconductor layer, a metal layer, and a bonding layer provided between the semiconductor layer and the metal layer, the bonding layer including a plurality of silver particles, and the bonding layer including a region containing gold existing between the plurality of silver particles.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: October 4, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Makoto Mizukami, Tatsuya Hirakawa, Tomohiro Iguchi
  • Publication number: 20210351161
    Abstract: According to an embodiment, provided is a semiconductor device includes an insulating substrate; a first main terminal; a second main terminal; an output terminal; a first metal layer connected to the first main terminal; a second metal layer connected to the second main terminal; a third metal layer disposed between the first metal layer and the second metal layer and connected to the output terminal; a first semiconductor chip and a second semiconductor chip provided on the first metal layer; and a third semiconductor chip and a fourth semiconductor chip provided on the third metal layer. The second metal layer includes a first slit. Alternatively, the third metal layer includes a second slit.
    Type: Application
    Filed: March 11, 2021
    Publication date: November 11, 2021
    Inventor: Tomohiro Iguchi
  • Publication number: 20210305204
    Abstract: A semiconductor device according to an embodiment includes a semiconductor layer, a metal layer, and a bonding layer provided between the semiconductor layer and the metal layer, the bonding layer including a plurality of silver particles, and the bonding layer including a region containing gold existing between the plurality of silver particles.
    Type: Application
    Filed: August 31, 2020
    Publication date: September 30, 2021
    Inventors: Makoto MIZUKAMI, Tatsuya HIRAKAWA, Tomohiro IGUCHI
  • Publication number: 20210305147
    Abstract: A semiconductor device according to an embodiment includes: an insulating substrate having a first metal layer and a second metal layer on a surface of the insulating substrate; a semiconductor chip including an upper electrode and a lower electrode, the upper electrode being electrically connected to the first metal layer, the lower electrode being electrically connected to the second metal layer; a first main terminal including a first end and a second end, the first end being electrically connected to the first metal layer; a second main terminal including a third end and a fourth end, the third end being electrically connected to the second metal layer; a first detection terminal being electrically connected between the first end and the second end of the first main terminal; and a second detection terminal being electrically connected to the first metal layer.
    Type: Application
    Filed: August 24, 2020
    Publication date: September 30, 2021
    Inventors: Tomohiro IGUCHI, Tatsuya HIRAKAWA
  • Patent number: 11098703
    Abstract: Provided is a variable displacement compressor capable of preventing intrusion of foreign matter into a second control valve. A variable displacement compressor 100 is equipped with a first control valve 300 controlling the opening degree of a supply passage 145, a check valve 350, a second control valve 400 controlling the opening degree of a discharge passage 146, and a back-pressure relief passage 147. The second control valve 400 has a back-pressure chamber 410 communicating with an intermediate supply passage 145b1, a valve chamber 420 in which a valve hole 103d and a discharge hole 431a are open and which constitutes a part of the discharge passage 146, a dividing member 430 dividing the back-pressure chamber 410 and the valve chamber 420 from each other, and a spool 440.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: August 24, 2021
    Assignee: Sanden Automotive Components Corporation
    Inventors: Yukihiko Taguchi, Takashi Toida, Satoshi Terauchi, Tomohiro Iguchi, Yoshie Matsuzaki
  • Patent number: 11081412
    Abstract: A semiconductor device of embodiments includes a first semiconductor chip; a metal plate having a first plane and a second plane facing the first plane and including a first ceramic plate provided between the first plane and the second plane; and a first insulating board provided between the first semiconductor chip and the metal plate and facing the first plane, in which the first ceramic plate does not exist between the first semiconductor chip and the second plane.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: August 3, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Takenori Yamada, Tomohiro Iguchi
  • Publication number: 20210082781
    Abstract: A semiconductor device of embodiments includes a first semiconductor chip; a metal plate having a first plane and a second plane facing the first plane and including a first ceramic plate provided between the first plane and the second plane; and a first insulating board provided between the first semiconductor chip and the metal plate and facing the first plane, in which the first ceramic plate does not exist between the first semiconductor chip and the second plane.
    Type: Application
    Filed: February 20, 2020
    Publication date: March 18, 2021
    Inventors: Takenori Yamada, Tomohiro Iguchi
  • Patent number: 10727209
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor element, a first element insulating part, and an insulating sealing member. The first semiconductor element includes a first semiconductor chip and a first chip electrode electrically connected to the first semiconductor chip. The first semiconductor chip has a first surface crossing a first direction, a second surface crossing the first direction and distant from the first surface, and a third surface between the first and second surfaces. The first chip electrode is disposed on the first surface. The first element insulating part includes a first portion and a second portion continuous to the first portion. The insulating sealing member includes a third portion and a fourth portion continuous to the third portion. The first portion is between the first surface and the third portion, and the second portion is between the third surface and the fourth portion.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: July 28, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomohiro Iguchi, Akiya Kimura, Akihiro Sasaki
  • Publication number: 20200095986
    Abstract: Provided is a variable displacement compressor capable of preventing intrusion of foreign matter into a second control valve. A variable displacement compressor 100 is equipped with a first control valve 300 controlling the opening degree of a supply passage 145, a check valve 350, a second control valve 400 controlling the opening degree of a discharge passage 146, and a back-pressure relief passage 147. The second control valve 400 has a back-pressure chamber 410 communicating with an intermediate supply passage 145b1, a valve chamber 420 in which a valve hole 103d and a discharge hole 431a are open and which constitutes a part of the discharge passage 146, a dividing member 430 dividing the back-pressure chamber 410 and the valve chamber 420 from each other, and a spool 440.
    Type: Application
    Filed: February 9, 2018
    Publication date: March 26, 2020
    Inventors: Yukihiko TAGUCHI, Takashi TOIDA, Satoshi TERAUCHI, Tomohiro IGUCHI, Yoshie MATSUZAKI
  • Patent number: 10410976
    Abstract: A method of manufacturing a semiconductor chip according to an embodiment includes forming on a semiconductor substrate a plurality of etching masks each including a protection film to demarcate a plurality of first regions of the substrate protected by the plurality of etching masks and a second region as an exposed region of the substrate, and anisotropically removing the second region by a chemical etching process to form a plurality of grooves each including a side wall at least partially located in the same plane as an end face of the etching mask and a bottom portion reaching a back surface of the substrate, thereby singulating the semiconductor substrate into a plurality of chip main bodies corresponding to the plurality of first regions.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: September 10, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yusaku Asano, Kazuhito Higuchi, Taizo Tomioka, Tomohiro Iguchi
  • Patent number: 10199365
    Abstract: According to one embodiment, a semiconductor module includes a first circuit component, a first connection member, and a first wire. The first circuit component includes a first substrate, a first conductive layer, a first switching device, and a first diode. The first substrate has an insulation property. The first connection member is provided on a first electrode of the first switching device and the fourth electrode of the first diode, and has a conductive property. The first wire connects the first conductive layer and the first connection member.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: February 5, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akiya Kimura, Tomohiro Iguchi, Akihiro Sasaki
  • Publication number: 20190035770
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor element, a first element insulating part, and an insulating sealing member. The first semiconductor element includes a first semiconductor chip and a first chip electrode electrically connected to the first semiconductor chip. The first semiconductor chip has a first surface crossing a first direction, a second surface crossing the first direction and distant from the first surface, and a third surface between the first and second surfaces. The first chip electrode is disposed on the first surface. The first element insulating part includes a first portion and a second portion continuous to the first portion. The insulating sealing member includes a third portion and a fourth portion continuous to the third portion. The first portion is between the first surface and the third portion, and the second portion is between the third surface and the fourth portion.
    Type: Application
    Filed: May 21, 2018
    Publication date: January 31, 2019
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomohiro IGUCHI, Akiya KIMURA, Akihiro SASAKI