Patents by Inventor Tomohiro Iguchi

Tomohiro Iguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180308833
    Abstract: A semiconductor device includes a first semiconductor chip, a second semiconductor chip, a metal substrate, an insulating substrate, a first bonding member, and a second bonding member. The metal substrate is spaced from the first and the second semiconductor chips in a first direction crossing a direction from the first semiconductor chip to the second semiconductor chip. The insulating substrate is provided between the first semiconductor chip and the metal substrate and between the second semiconductor chip and the metal substrate. The first bonding member is provided between the metal substrate and the insulating substrate. Part of the first bonding member is located between the first semiconductor chip and the metal substrate. The second bonding member is provided between the metal substrate and the insulating substrate. Part of the second bonding member is located between the second semiconductor chip and the metal substrate.
    Type: Application
    Filed: March 12, 2018
    Publication date: October 25, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Sasaki, Tomohiro Iguchi, Akiya Kimura
  • Patent number: 10086478
    Abstract: According to one embodiment, a metallic particle paste includes a polar solvent and particles dispersed in the polar solvent and containing a first metal. A second metal different from the first metal is dissolved in the polar solvent.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: October 2, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Daisuke Hiratsuka, Tomohiro Iguchi, Masayuki Uchida
  • Publication number: 20180226389
    Abstract: According to one embodiment, a semiconductor module includes a first circuit component, a first connection member, and a first wire. The first circuit component includes a first substrate, a first conductive layer, a first switching device, and a first diode. The first substrate has an insulation property. The first connection member is provided on a first electrode of the first switching device and the fourth electrode of the first diode, and has a conductive property. The first wire connects the first conductive layer and the first connection member.
    Type: Application
    Filed: February 2, 2018
    Publication date: August 9, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Akiya KIMURA, Tomohiro Iguchi, Akihiro Sasaki
  • Publication number: 20170170150
    Abstract: A semiconductor module according to an embodiment has first and second wiring portions, first semiconductor devices and second semiconductor devices. The second wiring portion is provided to oppose the first wiring portion. The third wiring portion is provided to oppose the first wiring portion. The first semiconductor devices are provided between the first wiring portion and the second wiring portion. Each of the first semiconductor devices has a first switching element, and an input terminal or an output terminal of the first switching element is electrically connected with the first wiring portion. The second semiconductor devices are provided between the first wiring portion and the third wiring portion. Each of the second semiconductor devices has a second switching element, and an output or input terminal of the second switching element is electrically connected with the first wiring portion in a manner contrary to the first switching element.
    Type: Application
    Filed: December 13, 2016
    Publication date: June 15, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tomohiro IGUCHI, Akihiro Sasaki, Tetsuya Yamamoto, Takashi Togasaki
  • Publication number: 20170050842
    Abstract: According to one embodiment, a printed wiring board includes a first magnetic layer, a second magnetic layer, an insulating layer, a first conductor layer, and a second conductor layer. The insulating layer is provided between the first magnetic layer and the second magnetic layer. The first conductor layer is provided between the insulating layer and the first magnetic layer. The second conductor layer is provided between the insulating layer and the second magnetic layer.
    Type: Application
    Filed: August 19, 2016
    Publication date: February 23, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiju YAMADA, Kazuo SHIMOKAWA, Tomohiro IGUCHI, Michiko HARA, Motomichi SHIBANO
  • Publication number: 20160358863
    Abstract: A method of manufacturing a semiconductor chip according to an embodiment includes forming on a semiconductor substrate a plurality of etching masks each including a protection film to demarcate a plurality of first regions of the substrate protected by the plurality of etching masks and a second region as an exposed region of the substrate, and anisotropically removing the second region by a chemical etching process to form a plurality of grooves each including a side wall at least partially located in the same plane as an end face of the etching mask and a bottom portion reaching a back surface of the substrate, thereby singulating the semiconductor substrate into a plurality of chip main bodies corresponding to the plurality of first regions.
    Type: Application
    Filed: August 18, 2016
    Publication date: December 8, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yusaku ASANO, Kazuhito HIGUCHI, Taizo TOMIOKA, Tomohiro IGUCHI
  • Patent number: 9460967
    Abstract: A method of manufacturing a semiconductor chip according to an embodiment includes forming on a semiconductor substrate a plurality of etching masks each including a protection film to demarcate a plurality of first regions of the substrate protected by the plurality of etching masks and a second region as an exposed region of the substrate, and anisotropically removing the second region by a chemical etching process to form a plurality of grooves each including a side wall at least partially located in the same plane as an end face of the etching mask and a bottom portion reaching a back surface of the substrate, thereby singulating the semiconductor substrate into a plurality of chip main bodies corresponding to the plurality of first regions.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: October 4, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yusaku Asano, Kazuhito Higuchi, Taizo Tomioka, Tomohiro Iguchi
  • Publication number: 20160190032
    Abstract: According to an embodiment, a wiring board includes an insulating board including a heat transfer region made of silicon nitride and having a thickness in a range between 0.2 mm and 1 mm; and a wiring layer including a pad stacked on the heat transfer region and made of a metal material having a thickness of 1.5 mm or more.
    Type: Application
    Filed: December 11, 2015
    Publication date: June 30, 2016
    Inventors: Kazuya Kodani, Yuta Ichikura, Nobumitsu Tada, Hiroaki Ito, Toshiharu Ohbu, Taihei Koyama, Kazuaki Yuuki, Yosuke Nakazawa, Atsushi Yamamoto, Makoto Otani, Kazuhiro Ueda, Tomohiro Iguchi
  • Publication number: 20160035657
    Abstract: According to one embodiment, a semiconductor device includes a first base portion, a second base portion, a third base portion, and a semiconductor element. A first end portion of the first base portion is positioned closer to a side on which the semiconductor element is provided than a second end portion of the first base portion. A third end portion of the second base portion is positioned closer to the side on which the semiconductor element is provided than a fourth end portion of the second base portion. A fifth end portion of the third base portion is positioned closer to the side on which the semiconductor element is provided than a sixth end portion of the third base portion in the third direction.
    Type: Application
    Filed: July 1, 2015
    Publication date: February 4, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Taizo TOMIOKA, Tomohiro IGUCHI, Takahiro AIZAWA
  • Patent number: 9202757
    Abstract: According to one embodiment, a semiconductor module includes: a first circuit component: a second circuit component; and a third circuit component. The first circuit component includes: an insulating first substrate; a first conductive layer; a first switching element; and a first diode. The second circuit component includes: an insulating second substrate; a second conductive layer; a second switching element; and a second diode. The second circuit component is disposed between the first circuit component and the third circuit component. The third circuit component includes: an insulating third substrate; a third conductive layer provided on the third substrate and including a third element mounting unit; a third switching element provided on the third element mounting unit; and a third diode provided on the third element mounting unit. A direction from the third switching element toward the third diode is an opposite direction to the first direction.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: December 1, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomohiro Iguchi, Masayuki Uchida, Daisuke Hiratsuka, Masako Fukumitsu
  • Publication number: 20150130028
    Abstract: A method of manufacturing a semiconductor chip according to an embodiment includes forming on a semiconductor substrate a plurality of etching masks each including a protection film to demarcate a plurality of first regions of the substrate protected by the plurality of etching masks and a second region as an exposed region of the substrate, and anisotropically removing the second region by a chemical etching process to form a plurality of grooves each including a side wall at least partially located in the same plane as an end face of the etching mask and a bottom portion reaching a back surface of the substrate, thereby singulating the semiconductor substrate into a plurality of chip main bodies corresponding to the plurality of first regions.
    Type: Application
    Filed: November 13, 2014
    Publication date: May 14, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yusaku ASANO, Kazuhito Higuchi, Taizo Tomioka, Tomohiro Iguchi
  • Publication number: 20150076516
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor element and a metal film. The semiconductor element has a first surface and a second surface opposite to the first surface. The metal film is provided above the second surface of the semiconductor element. The metal film includes Cr.
    Type: Application
    Filed: March 10, 2014
    Publication date: March 19, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yuuji Hisazato, Hiroki Sekiya, Yo Sasaki, Kazuya Kodani, Nobumitsu Tada, Hitoshi Matsumura, Tomohiro Iguchi
  • Publication number: 20150069638
    Abstract: According to one embodiment, a metallic particle paste includes a polar solvent and particles dispersed in the polar solvent and containing a first metal. A second metal different from the first metal is dissolved in the polar solvent.
    Type: Application
    Filed: July 22, 2014
    Publication date: March 12, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Daisuke HIRATSUKA, Tomohiro IGUCHI, Masayuki UCHIDA
  • Patent number: 8975732
    Abstract: According to one embodiment, a semiconductor device includes, a chip including a first chip electrode on a first surface on one side, and a second chip electrode on a second surface on the other side, an electrically conductive frame provided on a side periphery of the chip, a rewiring configured to electrically connect the second chip electrode and the electrically conductive frame on the other side of the chip, and an insulation side portion provided between the electrically conductive frame and the side periphery of the chip.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Tojo, Kazuhito Higuchi, Tomohiro Iguchi, Masako Fukumitsu, Daisuke Hiratsuka, Akihiro Sasaki, Masayuki Uchida
  • Publication number: 20140284797
    Abstract: A method for fabricating a power semiconductor device that comprises a base substrate with a conductive layer on a surface of the base substrate and semiconductor components mounted on the base substrate includes forming a hardened layer on the surface of the conductive layer before mounting a semiconductor component on the base substrate. The forming of the hardened layer may optionally be performed using a peening process, for example, a shot peening process, a laser peening process, or an ultrasonic peening process. The conductive layer may comprise a metal such as, for example, aluminum or copper.
    Type: Application
    Filed: September 3, 2013
    Publication date: September 25, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuuji HISAZATO, Hiroki SEKIYA, Yo SASAKI, Kazuya KODANI, Nobumitsu TADA, Hitoshi MATSUMURA, Tomohiro IGUCHI
  • Publication number: 20140264435
    Abstract: According to one embodiment, a semiconductor module includes: a first circuit component: a second circuit component; and a third circuit component. The first circuit component includes: an insulating first substrate; a first conductive layer; a first switching element; and a first diode. The second circuit component includes: an insulating second substrate; a second conductive layer; a second switching element; and a second diode. The second circuit component is disposed between the first circuit component and the third circuit component. The third circuit component includes: an insulating third substrate; a third conductive layer provided on the third substrate and including a third element mounting unit; a third switching element provided on the third element mounting unit; and a third diode provided on the third element mounting unit. A direction from the third switching element toward the third diode is an opposite direction to the first direction.
    Type: Application
    Filed: September 16, 2013
    Publication date: September 18, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomohiro IGUCHI, Masayuki Uchida, Daisuke Hiratsuka, Masako Fukumitsu
  • Publication number: 20130241040
    Abstract: According to one embodiment, a semiconductor device includes, a chip including a first chip electrode on a first surface on one side, and a second chip electrode on a second surface on the other side, an electrically conductive frame provided on a side periphery of the chip, a rewiring configured to electrically connect the second chip electrode and the electrically conductive frame on the other side of the chip, and an insulation side portion provided between the electrically conductive frame and the side periphery of the chip.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 19, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akira Tojo, Kazuhito Higuchi, Tomohiro Iguchi, Masako Fukumitsu, Daisuke Hiratsuka, Akihiro Sasaki, Masayuki Uchida
  • Patent number: 8378479
    Abstract: According to an aspect of the present invention, there is provided a semiconductor device, including a semiconductor chip including a first electrode and a second electrode of a semiconductor element, the first electrode and the second electrode being configured on a first surface and a second surface of the semiconductor chip, an encapsulating material encapsulating the semiconductor chip, the surface portion being other than regions, each of the regions connecting with the first second electrodes, each of inner electrodes being connected with the first or the second electrodes, a thickness of the inner electrode from the first surface or the second surface being the same thickness as the encapsulating material from the first surface or the second surface, respectively, outer electrodes, each of the outer electrodes being formed on the encapsulating material and connected with the inner electrode, a width of the outer electrode being at least wider than a width of the semiconductor chip, and outer plating ma
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: February 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Tojo, Tomoyuki Kitani, Kazuhito Higuchi, Masako Fukumitsu, Tomohiro Iguchi, Hideo Nishiuchi, Kyoto Kato
  • Patent number: 8241937
    Abstract: An optical semiconductor device includes a light emitting element having a first surface and a second surface, the first surface having a first electrode provided thereon, the second surface being located on the opposite side from the first surface and having a second electrode provided thereon; a first conductive member connected to the first surface; a second conductive member connected to the second surface; a first external electrode connected to the first conductive member; a second external electrode connected to the second conductive member; and an enclosure sealing the light emitting element, the first conductive member, and the second conductive member between the first external electrode and the second external electrode, and being configured to transmit light emitted from the light emitting element.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: August 14, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiko Happoya, Kazuhito Higuchi, Tomohiro Iguchi, Kazuo Shimokawa, Takashi Koyanagawa, Michinobu Inoue, Izuru Komatsu, Hisashi Ito
  • Patent number: 8193643
    Abstract: According to an aspect of the present invention, there is provided a semiconductor device, including a semiconductor chip including a semiconductor element, a first electrode of the semiconductor chip being configured on a first surface of the semiconductor element, a second electrode of the semiconductor element being configured on a second surface opposed to the first surface of the semiconductor chip, an encapsulating material encapsulating the semiconductor chip, a first hole and a second hole being configured in the encapsulating material, a portion of the first electrode and a portion of the second electrode being exposed, a first conductive material being connected to the first surface of the semiconductor chip via the first hole, a second conductive material being connected to the second surface of the semiconductor chip via the second hole, and a plating film covering five surfaces of the first conductive material other than one surface contacting with the encapsulating material and five surfaces of
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: June 5, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Tojo, Tomoyuki Kitani, Tomohiro Iguchi, Takahiro Aizawa, Hideo Nishiuchi, Masako Fukumitsu