Abstract: A jet engine is provided which can efficiently pressurize fuel. A jet engine 2 includes a pump 110 that heats fuel, a heating conduit 120 that heats the pressurized fuel, a fuel turbine 130 that provides mechanical power to the pump, and an electric rotating machine 140. When a given condition is not satisfied, the electric rotating machine 140 provides mechanical power to the fuel turbine 130. When the given condition is satisfied, the fuel that has passed through the heating conduit 120 before combustion flows into the fuel turbine 130 to provide mechanical power to the fuel turbine 130.

Abstract: A method of manufacturing a sealed electronic component, which can seal a housing in a high-vacuum state while preventing enclosure of a gas within the housing, as well as achieving the improvement in manufacturing efficiency. According to the method, after forming an unwelded section by a primary welding process step, including a first beam irradiation process step and a second beam irradiation process step, annealing treatment is performed in an annealing process step by irradiating an electron beam to a predetermined portion on a locus of the electron beam formed in the first beam irradiation process step. The locus may be on a housing or a lid.

Abstract: After forming an unwelded section by a primary welding process step (S203) including a first beam irradiation process step (S203a) and a second beam irradiation process step (S203b), annealing treatment is performed in an annealing process step (S204) by irradiating an electron beam to a predetermined portion on a locus of the electron beam formed in the first beam irradiation process step (S203a). Thereby, there is provided a manufacturing method of a sealed electronic component, which can seal a housing in a high-vacuum state while preventing enclosure of a gas within the housing, as well as achieving the improvement in manufacturing efficiency.

Abstract: An internal address signal corresponding to data to be written into a memory cell is held in a latch circuit. The held internal address signal is selected by a multiplexer in the next writing operation and applied to a decoder. Write data is taken in and held by a latch circuit during the period in which data is not being read out from the memory cell array. A comparator compares the held internal address signal and an internal address signal for reading data. If a matching is found between them, the multiplexer outputs data from the latch circuit for externally output. Accordingly, delay of a writing operation following a reading operation can be eliminated without increasing chip cost, package cost, and system cost, as a result high speed operation of cache memories is achieved and the speed performance of computers of various levels such as supercomputer, large size calculators, work stations and personal computers can be improved.

Abstract: A computer includes a storage device having a plurality of memory cells, being operable to output data stored in the memory cell corresponding to an address signal, and being operable to output a data output fixing signal attaining a predetermined level in response to output of the data, and a processing device operable to apply the address signal to the storage device, take in the data from the storage device in response to the fact that the data output fixing signal attains the predetermined level, and perform processing in accordance with the data. The storage device and the processing device may be formed on a single chip. The processing device can take in and process the data whenever the data output fixing signal is output. When the storage device operates under conditions better than the worst conditions, data processing can be performed before elapse of a maximum access time determined in a specification prescribed taking the worst conditions into consideration.

Abstract: An internal address signal corresponding to data to be written into a memory cell is held in a latch circuit. The held internal address signal is selected by a multiplexer in the next writing operation and applied to a decoder. Write data is taken in and held by the latch circuit during the period in which data is not being read out from the memory cell array. A comparator compares the held internal address signal and an internal address signal for reading data. If a matching is found between them, the multiplexer outputs data from the latch circuit for externally output. Accordingly, delay of a writing operation following a reading operation can be eliminated without increasing chip cost, package cost, and system cost, as a result high speed operation of cache memories is achieved and the speed performance of computers of various levels such as supercomputer, large size calculator, work station and personal computer can be improved.

Abstract: An internal address signal corresponding to data to be written into a memory cell is held in a latch circuit. The held internal address signal is selected by a multiplexer in the next writing operation and applied to a decoder. Write data is taken in and held by the latch circuit during the period in which data is not being read out from the memory cell array. A comparator compares the held internal address signal and an internal address signal for reading data. If a matching is found between them, the multiplexer outputs data from the latch circuit for external output. Accordingly, delay of a writing operation following a reading operation can be eliminated without increasing chip cost, package cost, and system cost, as a result high speed operation of cache memories is achieved and the speed performance of computers of various levels such as supercomputers, large size calculators, work stations and personal computers can be improved.

Abstract: A computer includes a storage device having a plurality of memory cells, being operable to output data stored in the memory cell corresponding to an address signal, and being operable to output a data output fixing signal attaining a predetermined level in response to output of the data, and a processing device operable to apply the address signal to the storage device, take in the data from the storage device in response to the fact that the data output fixing signal attains the predetermined level, and perform processing in accordance with the data. The storage device and the processing device may be formed on a single chip. The processing device can take in and process the data whenever the data output fixing signal is output. When the storage device operates under conditions better than the worst conditions, data processing can be performed before elapse of a maximum access time determined in a specification prescribed taking the worst conditions into consideration.

Abstract: In a semiconductor memory device having a plurality of data input/output pins, control pins (e.g. address pins and external control signal pins) are arranged parallel to each other on a chip. The plurality of data input/output pins are divided into a plurality of groups. Each group has a specific data input/output pin. The specific data input/output pin is lined up with the control pins. In a test mode, a signal is written into all memory cells by applying the signal to the specific data input/output pin. In addition, whether the signals read from all memory cells are correct or not is determined using the specific data input/output pin.

Abstract: A semiconductor memory for operating in burst mode. The memory has a memory cell array divided into a plurality of memory blocks, a plurality of (e.g., 2) output registers each including a plurality of output data retaining blocks corresponding to the multiple memory blocks, and a burst counter unit. The output registers alternately receive data transferred from the memory cell array. In accordance with the result of counting by the burst counter unit, the data retained in the output registers is output alternately in bursts, whereby the speed of data read operation in the memory is boosted regardless of the operating speed of the memory cell array therein.

Abstract: A semiconductor memory for operating in burst mode. The memory has a memory cell array divided into a plurality of memory blocks, a plurality of (e.g., 2) output registers each including a plurality of output data retaining blocks corresponding to the multiple memory blocks, and a burst counter unit. The output registers alternately receive data transferred from the memory cell array. In accordance with the result of counting by the burst counter unit, the data retained in the output registers is output alternately in bursts, whereby the speed of data read operation in the memory is boosted regardless of the operating speed of the memory cell array therein.

Abstract: In a synchronous semiconductor memory device, a predecoder is provided between a former stage address input register formed of first latch circuits and a latter stage address input register formed of second latch circuits. The first and second latch circuits operate in response to first and second internal clock signals complementary to each other. A predecode signal can be latched by the second latch circuit even when the generation of the predecode signal is not in time for the rise of the second internal dock signal due to delay of the input of an external address signal. Accordingly, the set up time for the external address signal can be reduced.

Abstract: An internal address signal corresponding to data to be written into a memory cell is held in a latch circuit. The held internal address signal is selected by a multiplexer in the next writing operation and applied to a decoder. Write data is taken in and held by the latch circuit during the period in which data is not being read out from the memory cell array. A comparator compares the held internal address signal and an internal address signal for reading data. If a matching is found between them, the multiplexer outputs data from the latch circuit for external output. Accordingly, delay of a writing operation following a reading operation can be eliminated without increasing chip cost, package cost, and system cost, as a result high speed operation of cache memories is achieved and the speed performance of computers of various levels such as supercomputers, large size calculators, work stations and personal computers can be improved.

Abstract: A high voltage generation circuit includes an inductor, a PN diode, a capacitor and a transistor. A high voltage sampling/division circuit, a control register, a voltage comparator, a counter, a pulse generation circuit and a ring oscillator in the high voltage generation circuit detect whether voltage generated through the capacitor is a desired high voltage or not and generates a pulse signal which controls ON/OFF of the transistor. Accordingly, a path of current flowing into the capacitor is changed and the generated voltage is digitally adjusted.

Abstract: An output buffer is connected to a first power supply line and a first ground line, and a strobe buffer is connected to a second power supply line and a second ground line. The first power supply line is connected to a first pad, the first ground line is connected to a second pad, the second power supply line is connected to a third pad, and the second ground line is connected to a fourth pad, respectively. The first and second power supply lines are not connected inside the chip, and the first and second ground lines are not connected inside the chip. The first and third pads are separately connected to the respective lead terminals, and the second and fourth pads are separately connected to the respective lead terminals.

Abstract: A semiconductor integrated circuit device with a high voltage detection circuit comprises a high voltage step-down circuit for stepping down a high voltage input and outputting the stepped-down voltage, a reference voltage generator for generating plural reference voltages, a reference voltage selector for selecting one of the plural reference voltages, a high voltage detection circuit for comparing the stepped down voltage with the selected reference voltage to detect a high voltage and a control circuit for controlling the voltage drop of the high voltage and selection of the plural reference voltages to set the high voltage to be detected by the high voltage detector.

Abstract: Memory cells which are adjacent to each other along a column direction share a bipolar transistor driving the potential level of a corresponding bit line. Other memory cells which are adjacent to each other in the column direction share another bipolar transistor driving the potential level of another corresponding bit line. Each bipolar transistor drives the potential level of the corresponding bit line in response to storage information of a selected memory cell, whereby data can be read at a high speed with a low power supply voltage.

Abstract: In a computer graphics apparatus, a main memory stores image data representing pixels on a raster scan display. A cache memory is provided for retaining a partial copy of the image data in the main memory. A computing unit processes the image data copied into the cache memory. A video cache memory acquires image data from the main memory and the cache memory. A graphics controller acquires image data from the video cache memory and outputs the image data to the raster scan display.

Abstract: A semiconductor memory device includes a plurality of external power supply pads P1 to P3. Connection between external power supply pads P1 to P3 and an external power supply is determined in accordance with the voltage of the external power supply to be used, and the connection is switched by bonding. External power supply of a high voltage level is connected to an external power supply pad P2 which is connected to VDC1 and VDC2. A circuit including memory cells operates using the voltage applied from VDC1 or external power supply pad P3, while a group of word line drivers operates using the voltage applied from VDC2 or external power supply pad P1. VDC1 down converts the external power supply voltage, and VDC2 down converts it in accordance with the level of the voltage of the external power supply voltage, and generates internal power supply voltages, respectively. Accordingly, a semiconductor memory device which operates adapted to different external power supplies can be obtained.

Abstract: A semiconductor memory device comprises first and second data buses. An output drive circuit adjusts the potentials at the first and second data buses in response to an internal read signal read from a memory cell. The gates of a PMOS transistor and an NMOS transistor forming an output stage corresponding to an output final stage are connected to ends of the first and second data buses, respectively. The potential of an output signal derived from the output stage loosely transits with a value decided by the capacitances of the first and second data buses. Thus, through rate control of the output signal can be implemented without reducing current drivability of the MOS transistors forming the output final stage.