Abstract: A cache memory device includes a plurality of memory cell arrays each including a plurality of memory cell rows, a plurality of first fuse elements each provided corresponding to each memory cell row and disconnected when the corresponding memory cell row is defective, and a plurality of second fuse elements each provided corresponding to each memory cell array and disconnected when the corresponding memory cell array is defective. As a result, the cache memory device can indicate that, when a bit line of a certain memory cell array is defective, the memory cell array is defective by disconnecting a second fuse element corresponding to the memory cell array.

Abstract: A circuit for repairing a defective memory cell is provided between a row or column decoder and a memory cell array. When the decoder has n output lines, the memory cell array includes at least (N+1) row or column lines, where n is an integer. The repair circuit includes connection circuit for connecting the output lines of the decoder to the row or column lines, and a circuit for defining the connection of the connection circuit. The connection circuit includes n switching elements each of which is operable to connect one output line of the decoder to at least two row or column lines. The defining circuit defines the connection path of each switching element such that the output lines of the decoder is connected in one to one correspondence to successively located row or column lines excluding a row or column line connecting a defective memory cell. The defining circuit includes a series of laser programmable fuse elements provided between an operation voltage supply and a ground line.

Abstract: A circuit for repairing a defective memory cell between a row or column decoder and a memory cell array. When the decoder has n output lines, the memory cell array includes at least (N+1) row or column lines, where n is an integer. The repair circuit includes connection circuit for connecting the output lines of the decoder to the row or column lines, and a circuit for defining the connection of the connection circuit. The connection circuit includes n switching elements each of which is operable to connect one output line of the decoder to at least two row or column lines. The defining circuit defines the connection path of each switching element such that the output lines of the decoder is connected in one to one correspondence to successively located row or column lines excluding a row or column line connecting a defective memory cell. The defining circuit includes a series of laser programmable fuse elements provided between an operation voltage supply and a ground line.

Abstract: A plurality of bit line signal IO lines L1, /L1 . . . Ln and /Ln are arranged on a memory cell array. These bit line signal IO lines are arranged to cross respective bit lines BL1, /BL1, . . . BLn and /BLn, and are connected to the corresponding bit lines, respectively. Each bit line signal IO line has an end extended to an end, in a direction perpendicular to the bit line, of a memory cell array, and is coupled at the end to a bit line peripheral circuit. Although bit line peripheral circuits could be arranged only at upper and lower ends of the bit lines in the prior art, the bit line peripheral circuits can be arranged also at the ends of the bit line signal IO lines in the invention. This can increase a degree of freedom in a layout for the bit line peripheral circuits, and thus the bit line peripheral circuits can be dispersedly arranged in a larger area.

Abstract: A semiconductor memory device includes a memory cell array composed of a plurality of memory cells. The memory cell array includes a plurality of word lines interconnecting the memory cells in the row direction and a plurality of bit line pairs interconnecting the memory cells in the column direction. One end of each bit line pair is connected to a clamping circuit, while the other end of each bit line pair is connected via a column select gate to a read/write circuit. Each bit line pair is bent about centrally in the two-dimensional form of a letter U and the clamping circuit and the column select gate are disposed alternately on one same straight line.

Abstract: A semiconductor storage device including a plurality of blocks each having an array of memory cells includes an exclusive OR circuit provided in each of the plurality of blocks for making a determination as to whether data written in memory cells in the blocks are normally read. Exclusive OR circuits of a plurality of memory cell array blocks are connected to an OR circuit. With an output signal from the OR circuit, a determination is made as to whether a plurality of memory cell array blocks are normal or not. Since test data from a plurality of memory cell array blocks are simultaneously examined by an OR circuit, a test time for the semiconductor storage device can be reduced.

Abstract: A plurality of bit line signal IO lines L1, /L1, . . . Ln and /Ln are arranged on a memory cell array. These bit line signal IO lines are arranged to cross respective bit lines BL1, /BL1, . . . BLn and /BLn, and are connected to the corresponding bit lines, respectively. Each bit line signal IO line has an end extended to an end, in a direction perpendicular to the bit line, of a memory cell array, and is coupled at the end to a bit line peripheral circuit. Although bit line peripheral circuits could be arranged only at upper and lower ends of the bit lines in the prior art, the bit line peripheral circuits can be arranged also at the ends of the bit line signal IO lines in the invention. This can increase a degree of freedom in a layout for the bit line peripheral circuits, and thus the bit line peripheral circuits can be dispersedly arranged in a larger area.

Abstract: A static type semiconductor memory device includes memory cells each including a pair of field effect transistors (FETs) each having a gate electrode cross-coupled to a drain region connected to a power source terminal by way of a load register. The memory device includes a semiconductor substrate of a first conductivity type, polycrystal silicon layers containing impurities of a second conductivity type and first and second FETs. The polycrystal silicon layers are formed with a spacing from one another for defining a channel region on the substrate. The first and second FETs are formed on the substrate and each includes source and drain regions of a second conductivity type and a gate electrode. The source and drain regions are formed below the polycrystal silicon layers by introducing impurities from the polycrystal silicon layers into the substrate. The gate electrode is formed on the channel region and the polycrystal silicon layers with a gate insulating film interposed.

Abstract: A semiconductor memory device changeable in word organization has a plurality of input/output terminals and a plurality of input terminals. Each of the plurality of input/output terminals and the plurality of input terminals are connected to an internal circuit via input/output buffers. These input/output buffers have identical structures and arrangements with identical input/output capacitance. The output buffer in the input/output buffer connected to an input terminal is coupled to a predetermined potential. The output buffer in the input/output buffer connected to an input/output terminal is activated by an output driver. The semiconductor memory device is generally set to a 1M word.times.1 bit organization. This semiconductor memory device may be set to a 256 k word.times.4 bit organization at the time of testing.

Abstract: A static type semiconductor memory device includes memory cells each including a pair of field effect transistors (FETs) each having a gate electrode cross-coupled to a drain region connected to a power source terminal by way of a load register. The memory device includes a semiconductor substrate of a first conductivity type, polycrystal silicon layers containing impurities of a second conductivity type and first and second FETs. The polycrystal silicon layers are formed with a spacing from one another for defining a channel region on the substrate. The first and second FETs are formed on the substrate and each includes source and drain regions of a second conductivity type and a gate electrode. The source and drain regions are formed below the polycrystal silicon layers by introducing impurities from the polycrystal silicon layers into the substrate. The gate electrode is formed on the channel region and the polycrystal silicon layers with a gate insulating film interposed.

Abstract: A circuit for repairing a defective memory cell is provided between a row or column decoder and a memory cell array. When the decoder has n output lines, the memory cell array includes at least (N+1) row or column lines, where n is an integer. The repair circuit includes connection circuit for connecting the output lines of the decoder to the row or column lines, and a circuit for defining the connection of the connection circuit. The connection circuit includes n switching elements each of which is operable to connect one output line of the decoder to at least two row or column lines. The defining circuit defines the connection path of each switching element such that the output lines of the decoder is connected in one to one correspondence to successively located row or column lines excluding a row or column line connecting a defective memory cell. The defining circuit includes a series of laser programmable fuse elements provided between an operation voltage supply and a ground line.

Abstract: A high resistance/load type memory cell of a static semiconductor memory device includes two load elements, two driver transistors, and two access transistors. The threshold voltage of each driver transistor is set at a high value so that the OFF resistance value of the driver transistor is 10 to 100 times the resistance value of each load resistance. The threshold voltage of each access transistor is set to be lower than the threshold voltage of each driver transistor so that the OFF resistance value of the access transistor is twice to 10 times the resistance value of each load resistance. Thus, power consumption in a standby state is reduced, while data holding characteristics of the memory cell are stabilized in selected and non-selected states.

Abstract: In a semiconductor integrated circuit device, an output MOSFET circuit includes a first N-type MOSFET and a first P-type MOSFET. The output circuit is controlled by two different control signals having two different levels to provide a signal at an output terminal at a junction between the two MOSFETs. An intermediate potential setting circuit includes a second N-type MOSFET and a second P-type MOSFET, and is followed by the output MOSFET circuit. The intermediate potential setting circuit sets the potential of the output terminal to an intermediate potential in accordance with an intermediate potential setting signal applied to the intermediate potential setting circuit prior to variation of the output. With this structure comsumption is reduced and high speed operation is made possible.

Abstract: In a static random access memory, when address signals change, one-shot pulses are responsively generated. A detection signal obtained by ORing the one-shot pulses is employed as an equalize signal. Potentials of a bit line pair is equalized in response to the equalize signal. A write inhibiting signal having a pulse width larger than that of the equalize signal is generated by a pulse width increasing circuit. A write operation of data is inhibited in response to the write inhibiting signal.

Abstract: A semiconductor memory device comprises a memory cell array, a row decoder, a column decoder, a plurality of sense amplifiers, a plurality of write circuits, a signal switching circuit, a plurality of input buffers, a plurality of output buffers and a plurality of terminals, which are formed on the same chip. A switching signal B1/B4 is applied to one of the plurality of terminals. The semiconductor memory device has a 256K word by 4 bit organization when the switching signal B1/B4 is at an "L" level and has a 1M word by 1 bit organization when the switching signal B1/B4 is at an "H" level. The word organization can be switched mainly by the signal switching circuit.

Abstract: A static semiconductor memory device comprises a plurality of memory cells each connected to complementary bit line pairs and to word lines, a row decoder for selecting any of the word lines, and a load and a transfer gate connected to the bit line pairs. When data "0" or "1" is written into all of the memory cells, the load is cut off from the bit lines by a current cutoff circuit, the bit lines are fixed to a predetermined potential by a current fixing circuit, and all of the word lines are driven by a word line driving circuit, so that all of the memory cells simultaneously enter a common state.

Abstract: In a semiconductor memory device in accordance with the present invention, a plurality of address signals (A.sub.1 to A.sub.N) are applied to address transition detection (ATD) circuits (31 to 3N) through input buffers (11 to 1N) and according to a level change in the address signals, a pulse signal (ATDi) is applied to an inverter (5) through any of MOS field-effect transistors (41 to 4N). The input level of the inverter (5) falls rapidly in response to the rise of the output level of the ATD circuits (31 to 3N) and rises slowly by the influence of a load device (40). A chip select transition detection (CSTD) circuit (6) generates a pulse signal (CST) in response to the change from a high level to a low level of a chip selection signal (CS) provided from a CS buffer (2). In response to the pulse signal (CST), a p channel MOS field-effect transistor (71) is turned on and a load device (72) is connected between the power supply potential and the input of the inverter (5).

Abstract: A storage node in each of memory cells in a static RAM is connected to a bit line through an accessing MOSFET. The accessing MOSFET has its gate connected to a word line. A word line driver comprising a level shifting N channel MOSFET and a CMOS inverter is connected to the word line. At the time of selecting the word line, a potential which is lower, by a threshold voltage of the MOSFET, than a power-supply potential is applied to the word line. Thus, a sub-threshold current flowing in the MOSFET connected between the storage node for storing data at a high level and the bit line to which data of a high level is read out becomes substantially small, so that a potential of the storage node for storing data of a high level is not lowered.

Abstract: Two resistors are connected in series between an input bonding electrode and an internal circuit, and respective conducting terminals of a first bipolar transistor are connected between the two resistors and a GND bonding electrode which is connected to the internal circuit. Respective conducting terminals of a second bipolar transistor are connected between the two resistors and a V.sub.DD bonding electrode which is connected to the internal circuit. Control terminals of the respective ones of the first and second bipolar transistors are connected to the GND bonding electrode respectively.

Abstract: A semiconductor memory device in accordance with the present invention operates in response to an address transition detection (ATD) signal for detecting a change in an x address as well as to a write enable signal WE to make the signal level on a selected word line vary according to the read mode and the write mode, whereby dissipation of electric power can be reduced.