Abstract: NMOS transistors as well as pMOS transistors are formed in an SOI layer. One of the impurity diffusion regions of the transistors are respectively connected. A longitudinal end of polysilicon layer extends in one direction to be connected to one of the impurity diffusion regions of transistor. A longitudinal end of a polysilicon layer extends in a direction which is opposite from the above mentioned one direction to be connected to one of the impurity diffusion regions of transistor. As a result, the area for a memory cell region in a static semiconductor memory device can be reduced, and the interconnection structure can be simplified.

Abstract: A computer includes a storage device having a plurality of memory cells, being operable to output data stored in the memory cell corresponding to an address signal, and being operable to output a data output fixing signal attaining a predetermined level in response to output of the data, and a processing device operable to apply the address signal to the storage device, take in the data from the storage device in response to the fact that the data output fixing signal attains the predetermined level, and perform processing in accordance with the data. The storage device and the processing device may be formed on a single chip. The processing device can take in and process the data whenever the data output fixing signal is output. When the storage device operates under conditions better than the worst conditions, data processing can be performed before elapse of a maximum access time determined in a specification prescribed taking the worst conditions into consideration.

Abstract: In an NPN bipolar transistor having a special structure in which each impurity region is formed by ion implantation, a width of a base region is significantly reduced, and therefore, current amplification factor hfe is increased, resulting in improvement in performance thereof. Furthermore, a Bi-CMOS transistor can be manufactured using a CMOS process. The use of the bipolar transistor having a special structure for a driving circuit allows implementation of a driving circuit having large driving force with slight increase in cost.

Abstract: A static type semiconductor memory device includes a main bit line pair, and a plurality of memory blocks connected to the main bit line pair. Each of the memory blocks includes a local bit line pair, a static memory connected to the local bit line pair, an amplifier which amplifies potential difference between the paired local bit lines, and a data transfer gate which transfers data between the local bit line pair and the main bit line pair.

Abstract: In repairing a defective memory cell of a data memory placed in a data memory region, a repairing circuit which employs a repairing method causing some access penalty but having high repairing efficiency is located in a redundant row region and a redundant column region in the data memory region. On the other hand, in repairing a defective memory cell of a tag memory placed in a tag memory region, a repairing circuit which employs a repairing method having low repairing efficiency but causing little access penalty is located in a redundant column region in the tag memory region. Accordingly, optimal repair of a defective memory cell can be achieved according to respective functions of the tag memory and the data memory.

Abstract: In a line configuration of each memory cell array employed in a semiconductor memory device, a pair of bit line signal input/output lines or a pair of input/output data lines for transmitting complementary signals are disposed on both sides of and adjacent the global word line so as to cancel the influence of the global word line. By these configurations, the number of shielded lines may be reduced and the width of each line and the interval between the lines are arrayed for preventing the respective lines from breaking or being short-circuited.

Abstract: A memory cell includes first and second driver transistors, first and second access transistors and first and second load elements, and in addition, first and second bipolar transistors. Accordingly, static noise margin is enlarged. The first bipolar transistor has its emitter formed in one of the source/drain regions of the first access transistor. The collector of the first bipolar transistor is the backgate terminal of the first access transistor. One of the source/drain regions of the first access transistor functions as the base of the first bipolar transistor. The same applies to the second bipolar transistor and the second access transistor. As the memory cell is structured in the above described manner, lower power supply potential can be used without the problem of latch up or increased area.

Abstract: A semiconductor memory device comprises a dynamic memory cell array, a static memory cell array, a plurality of word lines, a plurality of DRAM bit line pairs and a plurality of SRAM bit line pairs. The dynamic memory cell array comprises a plurality of dynamic memory cells arranged in the shape of a matrix. The static memory cell array is arranged adjacent to the dynamic memory cell array. The static memory cell array includes the static memory cells arranged in the shape of a matrix. A plurality of word lines are arranged in a plurality of rows. Each word line is connected to the dynamic and static memory cells arranged in the corresponding rows. A plurality of DRAM bit line pairs are arranged in a plurality of columns. Each DRAM bit line pair is connected to the dynamic memory cells. A plurality of SRAM bit line pairs are arranged in the other plurality of columns. Each SRAM bit line pair is connected to the static memory cells arranged in the corresponding columns.

Abstract: An internal address signal corresponding to data to be written into a memory cell is held in a latch circuit. The held internal address signal is selected by a multiplexer in the next writing operation and applied to a decoder. Write data is taken in and held by the latch circuit during the period in which data is not being read out from the memory cell array. A comparator compares the held internal address signal and an internal address signal for reading data. If a matching is found between them, the multiplexer outputs data from the latch circuit for external output. Accordingly, delay of a writing operation following a reading operation can be eliminated without increasing chip cost, package cost, and system cost, as a result high speed operation of cache memories is achieved and the speed performance of computers of various levels such as supercomputers, large size calculators, work stations and personal computers can be improved.

Abstract: Sense circuits are provided correspondingly to bit line pairs provided corresponding to memory cell columns, respectively. The sense circuit senses, amplifies and latches storage data of the selected memory cell, and information latched by the sense amplifier is rewritten into the selected memory cell after selection of the memory cell. Thereby, destruction of storage information of the memory cell is prevented.

Abstract: In a semiconductor memory cell array including word lines, bit lines, and a plurality of memory cells arranged at crossings between the word lines and the bit lines, the bit lines are grouped into odd and even numbered groups. A shift redundancy circuit is arranged between each group of odd or even bit lines and sense amplifier and write circuits for the purpose of shifting a defective memory cell to a redundant memory cell.

Abstract: A pair of driving bipolar transistors of a lateral type T1 and T2 have emitters coupled to a ground potential, collectors connected to a pair of highly resistive elements R1 and R2. Highly resistive elements R1 and R2 have respective other ends coupled to power supply potential V.sub.CC, and bases and collectors of transistors T1 and T2 are cross-connected to each other, thereby forming a flipflop circuit. Access MOS transistors Q3 and Q4 having a gate potential controlled by word line WL are each connected to form a conduction path between one of storage nodes A and B and one of the pair of bit lines BL and /BL.

Abstract: A semiconductor memory device comprises a dynamic memory cell array, a static memory cell array, a plurality of word lines, a plurality of DRAM bit line pairs and a plurality of SRAM bit line pairs. The dynamic memory cell array comprises a plurality of dynamic memory cells arranged in the shape of a matrix. The static memory cell array is arranged adjacent to the dynamic memory cell array. The static memory cell array includes the static memory cells arranged in the shape of a matrix. A plurality of word lines are arranged in a plurality of rows. Each word line is connected to the dynamic and static memory cells arranged in the corresponding rows. A plurality of DRAM bit line pairs are arranged in a plurality of columns. Each DRAM bit line pair is connected to the dynamic memory cells. A plurality of SRAM bit line pairs are arranged in the other plurality of columns. Each SRAM bit line pair is connected to the static memory cells arranged in the corresponding columns.

Abstract: A semiconductor memory device comprising a memory cell array, a row decoder, an input/output register train, a burst counter, an input/output bus, a refresh counter and a multiplexer. The memory cell array includes a plurality of word lines, a plurality of bit line pairs and a plurality of memory cells. The input/output register train has a plurality of registers corresponding to the bit line pairs. Each of the registers is connected to the corresponding bit line pair. The input/output bus inputs and outputs data to and from the register train in response to a signal from the burst counter. The multiplexer supplies the row decoder with an external address signal as an internal address signal. After data is transferred from any bit line pair to the register or before data is transferred from any register to the bit line pair, the multiplexer supplies the row decoder with a refresh address signal from the refresh counter in place of the external address signal.

Abstract: A sense amplifier portion provides a predetermined number of data among a plurality of data provided from a bit line pair to a multiplexer. A sense amplifier amplifies data provided from a redundancy bit line pair for output to the multiplexer. The multiplexer is controlled by a redundancy control burst counter. When a defect occurs in a memory cell array, the multiplexer provides data provided from the sense amplifier instead of data provided from the sense amplifier portion. When there is no defect, the multiplexer provides predetermined data using data provided from the sense amplifier portion.

Abstract: Bit lines which are adjacent to each other are connected to bit line signal input/output lines which are not adjacent to each other, via through holes. By this connection, data input/output lines, shield lines and a global word line are arranged between the through holes, whereby the distance between the through holes can be widened, minimum space between the bit lines can be widened, and therefore, higher integration of the memory array is realized.

Abstract: In a memory cell array, memory cells are formed in a matrix. Bit lines are formed to be connected to prescribed memory cells. Emitters of bipolar transistors are connected to bit lines. Bipolar transistors have their bases connected to each other, and further to precharge signal control means. Collector regions of bipolar transistors are connected to a power supply node. Bipolar transistors have a base region formed by introducing a p type impurity to the entire main surface of the semiconductor substrate, and n type impurity concentration included in the collector region immediately below the base region is at most 5.times.10.sup.18 cm.sup.-1. Consequently, a semiconductor memory device having a bipolar transistor which is capable of high speed operation and having high reliability can be manufactured at low cost.

Abstract: In the present invention, a row address processing circuit and a column address processing circuit operate in synchronism with an externally applied synchronous signal in a semiconductor memory device. The row address processing circuit and the column address processing circuit each include an address buffer and a decoder. The address buffer or decoder operates in synchronism with the synchronous signal.

Abstract: A semiconductor memory device includes a plurality of sense amplifiers for amplifying current changes which occur in corresponding bit line pairs in accordance with binary signals stored in activated memory cells. Each of the sense amplifiers includes first and second current mirror circuits for generating currents of the magnitudes respectively corresponding to currents flowing through a corresponding bit line pair, a storing circuit, responsive to a signal selecting a memory cell, for storing the currents generated by the first and second current mirror circuits before activation of the memory cell, or a difference between these currents, and a current supplying circuit, responsive to activation of the memory cell and based on the amount stored in the storing circuit, for supplying, to the first and second current mirror circuits, currents having a predetermined relationship with the currents having been generated by the first and second current mirror circuits before activation of the memory cell.

Abstract: An internal address signal corresponding to data to be written into a memory cell is held in a latch circuit. The held internal address signal is selected by a multiplexer in the next writing operation and applied to a decoder. Write data is taken in and held by the latch circuit during the period in which data is not being read out from the memory cell array. A comparator compares the held internal address signal and an internal address signal for reading data. If a matching is found between them, the multiplexer outputs data from the latch circuit for externally output. Accordingly, delay of a writing operation following a reading operation can be eliminated without increasing chip cost, package cost, and system cost, as a result high speed operation of cache memories is achieved and the speed performance of computers of various levels such as supercomputer, large size calculator, work station and personal computer can be improved.