Patents by Inventor Tomoki Inoue

Tomoki Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7185922
    Abstract: Anti-rotation device for a pipe and a connector has a pipe connecting portion and a connector connecting portion constructed integrally on the pipe connecting portion. The anti-rotation device is mounted on the pipe and the connector while the pipe connecting portion clips a straight tubular inserting side portion of the pipe in anti-rotating relation and the connector connecting portion is connected to the connector in anti-rotating relation. Thereby the pipe is connected to the connector in anti-rotating relation.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: March 6, 2007
    Assignee: Tokai Rubber Industries, Ltd.
    Inventors: Akira Takayanagi, Tomoki Inoue
  • Publication number: 20070040184
    Abstract: According to an embodiment of the invention, there is provided a semiconductor device comprising: a semiconductor element having a first main electrode, a second main electrode and a control electrode, a current flowing between the first and second main electrodes being controlled by a control signal which is input between the control electrode and the second main electrode; and a capacitor formed by providing an insulating layer between the second main electrode and the control electrode of the semiconductor element.
    Type: Application
    Filed: October 30, 2006
    Publication date: February 22, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koichi Sugiyama, Tomoki Inoue
  • Publication number: 20070040185
    Abstract: According to an embodiment of the invention, there is provided a semiconductor device comprising: a semiconductor element having a first main electrode, a second main electrode and a control electrode, a current flowing between the first and second main electrodes being controlled by a control signal which is input between the control electrode and the second main electrode; and a capacitor formed by providing an insulating layer between the second main electrode and the control electrode of the semiconductor element.
    Type: Application
    Filed: October 30, 2006
    Publication date: February 22, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koichi Sugiyama, Tomoki Inoue
  • Patent number: 7170106
    Abstract: A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.
    Type: Grant
    Filed: September 9, 2005
    Date of Patent: January 30, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masakazu Yamaguchi, Hideaki Ninomiya, Ichiro Omura, Tomoki Inoue
  • Publication number: 20060267129
    Abstract: A semiconductor device including a base layer of a first conductivity type having a first main surface and a second main surface opposite the first main surface, a first main electrode layer connected to the first main surface, control regions arranged inside grooves penetrating the first main electrode layer and reach inside the base layer, and a second main electrode layer of the first conductivity type and connected to the second main surface.
    Type: Application
    Filed: August 4, 2006
    Publication date: November 30, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tomoki Inoue, Koichi Sugiyama, Hideaki Ninomiya, Tsuneo Ogura
  • Patent number: 7141832
    Abstract: According to an embodiment of the invention, there is provided a semiconductor device comprising: a semiconductor element having a first main electrode, a second main electrode and a control electrode, a current flowing between the first and second main electrodes being controlled by a control signal which is input between the control electrode and the second main electrode; and a capacitor formed by providing an insulating layer between the second main electrode and the control electrode of the semiconductor element.
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: November 28, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Sugiyama, Tomoki Inoue
  • Patent number: 7119379
    Abstract: A semiconductor device disclosed herein comprises: a first base region which is of a first conductivity type; a second base region which is of a second conductivity type and which is selectively formed on a major surface of the first base region; a stopper region which is of a first conductivity type and which is formed on the major surface of the first base region, the stopper region being a predetermined distance away from the second base region and surrounding the second base region; and a ring region which is of a second conductivity type which is formed on the major surface of the first base region between the second base region and the stopper region, the ring region being spirally around the second base region and electrically connected to the second base region and the stopper region.
    Type: Grant
    Filed: October 22, 2003
    Date of Patent: October 10, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideaki Ninomiya, Tomoki Inoue
  • Publication number: 20060214199
    Abstract: A solid-state image sensing device provided with photoelectric conversion films stacked above a semiconductor substrate, comprising: first impurity regions as defined herein; second impurity regions as defined herein; signal charge reading regions as defined herein; and third impurity regions as defined herein.
    Type: Application
    Filed: March 8, 2006
    Publication date: September 28, 2006
    Inventors: Tomoki Inoue, Shinji Uya
  • Publication number: 20060202308
    Abstract: A semiconductor device comprises a first base layer of a first conductive type which has a first surface and a second surface; a second base layer of a second conductive type which is formed on the first surface; first and second gate electrodes which are formed by embedding an electrically conductive material into a plurality of trenches via gate insulating films, the plurality of trenches being formed such that bottoms of the trenches reach the first base layer; source layers of the first conductive type which are formed on a surface area of the second base layer so as to be adjacent to both side walls of the trench provided with the first gate electrode and one side wall of the trench provided with the second gate electrode, respectively; an emitter layer of the second conductive type which is formed on the second surface; emitter electrodes which are formed on the second base layer and the source layers; a collector electrode which is formed on the emitter layer; and first and second terminals which are e
    Type: Application
    Filed: May 16, 2006
    Publication date: September 14, 2006
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koichi Sugiyama, Tomoki Inoue, Hideaki Ninomiya, Masakazu Yamaguchi
  • Patent number: 7104571
    Abstract: The connector clip for verifying complete connection integrally includes a clip body of U-shape in cross-section to receive a tubular holding portion and a connection verifying portion of U-shape in cross-section to receive an opposite axial side of an annular verification projection with respect to the pipe. The connection verifying portion has a verifying body and a snap-fit portion. The clip body and the verifying body are connected via a connection part, while the verifying body and the snap-fit portion are connected via a joint part. Reinforcement ribs are formed along an entire circumference of outer surface of the verifying body.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: September 12, 2006
    Assignee: Tokai Rubber Industries, Ltd.
    Inventors: Tomoki Inoue, Kazuhito Kasahara
  • Publication number: 20060197151
    Abstract: A semiconductor device include a plurality of active element cells including first element regions of a first conductivity type and second element regions of a second conductivity type, the second element regions disposed between the first element regions; and isolation regions disposed between the active element cells so as to isolate the active element cells from each other, the isolation regions being filled with a plurality of semi-insulating particles including granular insulators covered by semiconductor films.
    Type: Application
    Filed: April 29, 2005
    Publication date: September 7, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hitoshi Kobayashi, Tomoki Inoue, Satoshi Aida, Yasushi Takahashi
  • Patent number: 7102207
    Abstract: A semiconductor device including a base layer of a first conductivity type having a first main surface and a second main surface opposite the first main surface, a first main electrode layer connected to the first main surface, control regions arranged inside grooves penetrating the first main electrode layer and reach inside the base layer, and a second main electrode layer of the first conductivity type and connected to the second main surface.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: September 5, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoki Inoue, Koichi Sugiyama, Hideaiki Ninomiya, Tsuneo Ogura
  • Patent number: 7078740
    Abstract: A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.
    Type: Grant
    Filed: May 12, 2004
    Date of Patent: July 18, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masakazu Yamaguchi, Hideaki Ninomiya, Ichiro Omura, Tomoki Inoue
  • Patent number: 7075168
    Abstract: A semiconductor device comprises a first base layer of a first conductive type which has a first surface and a second surface; a second base layer of a second conductive type which is formed on the first surface; first and second gate electrodes which are formed by embedding an electrically conductive material into a plurality of trenches via gate insulating films, the plurality of trenches being formed such that bottoms of the trenches reach the first base layer; source layers of the first conductive type which are formed on a surface area of the second base layer so as to be adjacent to both side walls of the trench provided with the first gate electrode and one side wall of the trench provided with the second gate electrode, respectively; an emitter layer of the second conductive type which is formed on the second surface; emitter electrodes which are formed on the second base layer and the source layers; a collector electrode which is formed on the emitter layer; and first and second terminals which are e
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: July 11, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Sugiyama, Tomoki Inoue, Hideaki Ninomiya, Masakazu Yamaguchi
  • Publication number: 20060131884
    Abstract: A piping structure for transporting a fuel arranged between an engine and a fuel tank, is constructed by use of a resin tube that is formed in a straight tubular shape. The resin tube is flexed and bent at one or more points along a longitudinal direction of the resin tube to define one or more bent portions and thereby is provided with a predetermined bent shape. The resin tube is fixed in a motor vehicle body so as to retain the bent portions and thereby assembled in the motor vehicle body.
    Type: Application
    Filed: December 15, 2005
    Publication date: June 22, 2006
    Inventors: Tomoki Inoue, Masayuki Sasagawa
  • Publication number: 20060134360
    Abstract: Piping unit for transporting a fuel is constructed by connecting a resin tube and a connector for connecting the resin tube to a mating pipe. The connector has a connector body including a retainer holding portion and a retainer for engaging with the mating pipe. The resin tube has a multilayered construction including an inner fuel barrier layer and an outer layer covered with a protective layer. The outer layer has a small outer diameter (od) up to 6 mm, the fuel barrier layer and the outer layer have a wall-thickness (t), and a ratio of the outer diameter (od)/the wall thickness (t) is in a range of 4 to 8.
    Type: Application
    Filed: December 15, 2005
    Publication date: June 22, 2006
    Inventors: Tomoki Inoue, Masayuki Sasagawa
  • Publication number: 20060113613
    Abstract: A semiconductor device disclosed herein comprises: a first base region which is of a first conductivity type; a second base region which is of a second conductivity type and which is selectively formed on a major surface of the first base region; a stopper region which is of a first conductivity type and which is formed on the major surface of the first base region, the stopper region being a predetermined distance away from the second base region and surrounding the second base region; and a ring region which is of a second conductivity type which is formed on the major surface of the first base region between the second base region and the stopper region, the ring region being spirally around the second base region and electrically connected to the second base region and the stopper region.
    Type: Application
    Filed: January 13, 2006
    Publication date: June 1, 2006
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hideaki Ninomiya, Tomoki Inoue
  • Publication number: 20060081903
    Abstract: An n channel type power MOS field effect transistor has silica particles buried in a bottom portion of a trench and a gate electrode buried in another portion of the trench. The gate electrode is in contact with the silica particles. A gap of the silica particles is not filled with the gate electrode.
    Type: Application
    Filed: October 14, 2005
    Publication date: April 20, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tomoki Inoue, Satoshi Aida, Yasushi Takahashi, Hitoshi Kobayashi
  • Publication number: 20060081919
    Abstract: A semiconductor device comprising: a first-conductivity-type base layer; a second-conductivity-type emitter layer formed on a first main surface of said first-conductivity-type base layer; a collector electrode formed in contact with a surface of said second-conductivity-type emitter layer; a second-conductivity-type base layer formed on a second main surface of said first-conductivity-type base layer; a plurality of trenches which extend through said second-conductivity-type base layer to reach a predetermined depth of said first-conductivity-type base layer, and has a longitudinal direction in one direction; a gate electrode formed in said trench via a gate insulating film; a first-conductivity-type emitter layer selectively formed in contact with side walls of said trench, in a surface portion of said second-conductivity-type base layer; an emitter electrode formed in contact with a surface of said second-conductivity-type base layer and a surface of said first-conductivity-type emitter layer; and a second
    Type: Application
    Filed: January 28, 2005
    Publication date: April 20, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tomoki Inoue, Hideaki Ninomiya, Koichi Sugiyama
  • Publication number: 20060070677
    Abstract: In a hose having a resin layer as an inner layer, a plasma treatment is performed on the inner surface of the inner layer and a connecting portion of an end part of the hose to thereby perform surface modification. Then, a sealing layer made of an elastic material is coated on and bonded to the inner surface of the connecting portion.
    Type: Application
    Filed: September 27, 2005
    Publication date: April 6, 2006
    Applicant: TOKAI RUBBER INDUSTRIES, LTD.
    Inventors: Tomoki Inoue, Kazutaka Katayama