Patents by Inventor Tomomitsu Risaki
Tomomitsu Risaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230307439Abstract: An ESD protection circuit is connected in parallel with an internal circuit operating at a predetermined operating voltage between a VDD terminal and a VSS terminal, and includes an NMOS transistor in which an N type high concentration drain region is connected to the VDD terminal and an N type high concentration source region is connected to the VSS terminal. A threshold voltage and a trigger voltage of a parasitic bipolar transistor of the NMOS transistor are higher than the operating voltage and lower than a breakdown voltage of the internal circuit and a breakdown voltage of a gate insulating film of the NMOS transistor.Type: ApplicationFiled: March 14, 2023Publication date: September 28, 2023Applicant: ABLIC Inc.Inventor: Tomomitsu RISAKI
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Patent number: 10497662Abstract: In order to inhibit forming cracks under a pad opening during ball bonding without increasing a chip size, a protective film includes a pad opening that exposes a part of a topmost layer metal film of the chip. A second metal film provided under the pad opening has a ring shape that defines a rectangular opening under the pad opening. The opening edge of the opening in the second metal film extends inwardly beyond the edge of the overlying pad opening. Vias connect the second metal film and the topmost layer metal film, and all of these vias are located outside the pad opening in plan view.Type: GrantFiled: January 24, 2018Date of Patent: December 3, 2019Assignee: ABLIC Inc.Inventors: Tomomitsu Risaki, Shoji Nakanishi, Hitomi Sakurai, Koichi Shimazaki
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Patent number: 10497706Abstract: Provided is a semiconductor device which has a non-volatile memory including: a semiconductor substrate; a tunnel insulating film formed on a surface of the semiconductor device; a floating gate formed on the tunnel insulating film; a memory cell transistor drain region and a memory cell transistor source region formed from the surface to an inside of the semiconductor substrate in a vicinity of both ends of the floating gate; a first interface formed between the semiconductor substrate and the tunnel insulating film; and a second interface formed between the floating gate and the tunnel insulating film. The first interface and the second interface form an uneven structure having a curvature that changes at an identical period with respect to a place in sectional view.Type: GrantFiled: February 26, 2019Date of Patent: December 3, 2019Assignee: ABLIC INC.Inventor: Tomomitsu Risaki
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Patent number: 10438944Abstract: When an ESD element is operated, for the purpose of suppressing heat generation and causing uniform current to flow through all channels of all transistors included in the ESD element, various substrate potentials existing in the transistors and the channels of a multi finger type ESD element are electrically connected via a low resistance substrate, and further, are set to a potential that is different from a Vss potential. In this manner, the current is uniformized and heat generation is suppressed through low voltage operation to improve an ESD tolerance.Type: GrantFiled: July 8, 2015Date of Patent: October 8, 2019Assignee: ABLIC Inc.Inventor: Tomomitsu Risaki
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Patent number: 10411137Abstract: Provided is a semiconductor device, which prevents unnecessary voltage drop in a MOS transistor that is connected in series in a location between a booster circuit and a memory main body portion, to thereby operate on a low voltage and improve the ON/OFF ratio so that chip size shrinking and memory performance improvement are accomplished simultaneously. In a semiconductor memory device including a memory transistor portion and a select transistor portion, at least the select transistor portion is formed of a fin-shaped single-crystal semiconductor thin film.Type: GrantFiled: November 28, 2016Date of Patent: September 10, 2019Assignee: ABLIC Inc.Inventor: Tomomitsu Risaki
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Publication number: 20190189623Abstract: Provided is a semiconductor device which has a non-volatile memory including: a semiconductor substrate; a tunnel insulating film formed on a surface of the semiconductor device; a floating gate formed on the tunnel insulating film; a memory cell transistor drain region and a memory cell transistor source region formed from the surface to an inside of the semiconductor substrate in a vicinity of both ends of the floating gate; a first interface formed between the semiconductor substrate and the tunnel insulating film; and a second interface formed between the floating gate and the tunnel insulating film. The first interface and the second interface form an uneven structure having a curvature that changes at an identical period with respect to a place in sectional view.Type: ApplicationFiled: February 26, 2019Publication date: June 20, 2019Inventor: Tomomitsu RISAKI
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Patent number: 10263003Abstract: Provided is a semiconductor device which has a non-volatile memory including: a semiconductor substrate; a tunnel insulating film formed on a surface of the semiconductor device; a floating gate formed on the tunnel insulating film; a memory cell transistor drain region and a memory cell transistor source region formed from the surface to an inside of the semiconductor substrate in a vicinity of both ends of the floating gate; a first interface formed between the semiconductor substrate and the tunnel insulating film; and a second interface formed between the floating gate and the tunnel insulating film. The first interface and the second interface form an uneven structure having a curvature that changes at an identical period with respect to a place in sectional view.Type: GrantFiled: March 21, 2018Date of Patent: April 16, 2019Assignee: ABLIC INC.Inventor: Tomomitsu Risaki
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Publication number: 20180294243Abstract: In order to inhibit forming cracks under a pad opening during ball bonding without increasing a chip size, a protective film includes a pad opening that exposes a part of a topmost layer metal film. A second metal film provided under the pad opening has a ring shape that defines a rectangular opening under the pad opening. The opening edge of the opening in the second metal film extends inwardly beyond the edge of the overlying pad opening.Type: ApplicationFiled: January 24, 2018Publication date: October 11, 2018Inventors: Tomomitsu RISAKI, Shoji NAKANISHI, Hitomi SAKURAI, Koichi SHIMAZAKI
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Publication number: 20180277548Abstract: Provided is a semiconductor device which has a non-volatile memory including: a semiconductor substrate; a tunnel insulating film formed on a surface of the semiconductor device; a floating gate formed on the tunnel insulating film; a memory cell transistor drain region and a memory cell transistor source region formed from the surface to an inside of the semiconductor substrate in a vicinity of both ends of the floating gate; a first interface formed between the semiconductor substrate and the tunnel insulating film; and a second interface formed between the floating gate and the tunnel insulating film. The first interface and the second interface form an uneven structure having a curvature that changes at an identical period with respect to a place in sectional view.Type: ApplicationFiled: March 21, 2018Publication date: September 27, 2018Inventor: Tomomitsu RISAKI
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Patent number: 9966476Abstract: A semiconductor memory device includes a first floating gate and a second floating gate of conductivity types with different polarities. Injection of electrons into the first floating gate via a tunnel insulating film is stored through a decrease in holes in a valence band of the second floating gate, and ejection of electrons from the first floating gate via the tunnel insulating film is stored through an increase in holes in the valence band of the second floating gate.Type: GrantFiled: May 4, 2016Date of Patent: May 8, 2018Assignee: SII Semiconductor CorporationInventor: Tomomitsu Risaki
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Publication number: 20170221878Abstract: When an ESD element is operated, for the purpose of suppressing heat generation and causing uniform current to flow through all channels of all transistors included in the ESD element, various substrate potentials existing in the transistors and the channels of a multi finger type ESD element are electrically connected via a low resistance substrate, and further, are set to a potential that is different from a Vss potential. In this manner, the current is uniformized and heat generation is suppressed through low voltage operation to improve an ESD tolerance.Type: ApplicationFiled: July 8, 2015Publication date: August 3, 2017Applicant: SII Semiconductor CorporationInventor: Tomomitsu RISAKI
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Publication number: 20170077309Abstract: Provided is a semiconductor device, which prevents unnecessary voltage drop in a MOS transistor that is connected in series in a location between a booster circuit and a memory main body portion, to thereby operate on a low voltage and improve the ON/OFF ratio so that chip size shrinking and memory performance improvement are accomplished simultaneously. In a semiconductor memory device including a memory transistor portion and a select transistor portion, at least the select transistor portion is formed of a fin-shaped single-crystal semiconductor thin film.Type: ApplicationFiled: November 28, 2016Publication date: March 16, 2017Inventor: Tomomitsu RISAKI
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Publication number: 20160329339Abstract: Provided is a semiconductor memory device including a floating gate formed of a semiconductor, which includes a first floating gate and a second floating gate being of conductivity types with different polarities. Injection of electrons into the first floating gate via a tunnel insulating film is stored through decrease in holes in a valence band of the second floating gate, and ejection of electrons from the first floating gate via the tunnel insulating film is stored through increase in holes in the valence band of the second floating gate.Type: ApplicationFiled: May 4, 2016Publication date: November 10, 2016Inventor: Tomomitsu RISAKI
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Patent number: 9343457Abstract: In order to provide a semiconductor device having a high ESD tolerance, a source wiring (32a) is formed on a gate (31) and a source (32) in a region of an NMOS transistor (30). The source wiring (32a) electrically connects the gate (31), the source (32), and a ground terminal. A drain wiring (33a) is formed on a drain (33) in the region of the NMOS transistor (30) . The drain wiring (33a) electrically connects the drain (33) and a pad (20) serving as an external connection electrode. Moreover, in the region of the NMOS transistor (30), the drain wiring (33a) has the same wiring width as the source wiring (32a).Type: GrantFiled: February 14, 2014Date of Patent: May 17, 2016Assignee: STI Semiconductor CorporationInventor: Tomomitsu Risaki
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Patent number: 9299629Abstract: A semiconductor device has a semiconductor substrate provided with a scribe region and an IC region. A first insulating film is disposed on the semiconductor substrate across the scribe region and the IC region. At least one separation groove is provided in the first insulating film in the scribe region. Side walls made of a plug metal film are formed only on respective lateral walls of the separation groove so that the plug metal film on the lateral walls does not extend out of the separation groove and does not exist on an upper surface of the first insulating film. A second insulating film covers at least the side walls formed on the respective lateral walls of the separation groove so that the side walls are disposed under the second insulating film.Type: GrantFiled: February 28, 2011Date of Patent: March 29, 2016Assignee: SEIKO INSTRUMENTS INC.Inventors: Tomomitsu Risaki, Shoji Nakanishi, Koichi Shimazaki
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Publication number: 20160020200Abstract: In order to provide a semiconductor device having a high ESD tolerance, a source wiring (32a) is formed on a gate (31) and a source (32) in a region of an NMOS transistor (30). The source wiring (32a) electrically connects the gate (31), the source (32), and a ground terminal. A drain wiring (33a) is formed on a drain (33) in the region of the NMOS transistor (30) . The drain wiring (33a) electrically connects the drain (33) and a pad (20) serving as an external connection electrode. Moreover, in the region of the NMOS transistor (30), the drain wiring (33a) has the same wiring width as the source wiring (32a).Type: ApplicationFiled: February 14, 2014Publication date: January 21, 2016Inventor: Tomomitsu RISAKI
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Patent number: 9177954Abstract: A semiconductor device has a semiconductor substrate and a breakdown voltage adjusting first conductivity type low concentration region provided on the semiconductor substrate. A second conductivity type high concentration region is provided near a surface within the breakdown voltage adjusting first conductivity type low concentration region so as to be surrounded by the first conductivity type low concentration region but not surrounded by any low concentration region other than the first conductivity type low concentration region. A first conductivity type high concentration region is provided on the surface within the breakdown voltage adjusting first conductivity type low concentration region without being held in contact with the second conductivity type high concentration region.Type: GrantFiled: April 3, 2013Date of Patent: November 3, 2015Assignee: SEIKO INSTRUMENTS INC.Inventor: Tomomitsu Risaki
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Publication number: 20150287714Abstract: A semiconductor device having a clamp diode has a breakdown voltage adjusting first conductivity type low concentration region provided on a semiconductor substrate. A second conductivity type high concentration region of circular shape is provided within the breakdown voltage adjusting first conductivity type low concentration region so as to be surrounded by the first conductivity type low concentration region but not surrounded by any other low concentration region. A first conductivity type high concentration region is provided within the first conductivity type low concentration region, without being held in contact with the second conductivity type high concentration region.Type: ApplicationFiled: June 22, 2015Publication date: October 8, 2015Inventor: Tomomitsu RISAKI
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Patent number: 9136263Abstract: Provided is a semiconductor device which uses a comb-like N-type MOS transistor as an ESD protection element and is capable of uniformly operating the entire comb-like N-type MOS transistor. By adjusting a length L of a gate electrode of the N-type MOS transistor used as the ESD protection element in accordance with the distance from a contact for fixing a substrate potential, which is provided on a guard ring around an outer periphery, respective portion of N-type MOS transistor represented as a comb teeth uniformly enter snap-back operation, permitting avoidance of local concentration of current and obtainment of a desired ESD tolerance.Type: GrantFiled: January 29, 2014Date of Patent: September 15, 2015Assignee: SEIKO INSTRUMENTS INC.Inventors: Takeshi Koyama, Tomomitsu Risaki
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Publication number: 20150221660Abstract: Provided is a semiconductor device, which prevents unnecessary voltage drop in a MOS transistor that is connected in series in a location between a booster circuit and a memory main body portion, to thereby operate on a low voltage and improve the ON/OFF ratio so that chip size shrinking and memory performance improvement are accomplished simultaneously. In a semiconductor memory device including a memory transistor portion and a select transistor portion, at least the select transistor portion is formed of a fin-shaped single-crystal semiconductor thin film.Type: ApplicationFiled: January 22, 2015Publication date: August 6, 2015Inventor: Tomomitsu RISAKI