Abstract: Provided is a semiconductor device comprising: a PW layer formed at a surface of a semiconductor substrate; an NW layer formed at the surface of the semiconductor substrate to be in contact with the PW layer; a p+ base layer formed at the surface of the semiconductor substrate in the PW layer; an n+ collector layer formed at the surface of the semiconductor substrate in the NW layer; an n+ emitter layer located between the p+ base layer and the n+ collector layer and formed at the surface of the semiconductor substrate in the PW layer; and an n± layer formed between the n+ collector layer and the PW layer to be in contact with the n+ collector layer.

Abstract: Provided is a semiconductor device capable of easily setting a holding voltage with a low trigger voltage by locally forming a P-type diffusion layer between N-type source and drain diffusion layers of an NMOS transistor having a conventional drain structure used as an electrostatic protective element of the semiconductor device.

Abstract: Provided is a semiconductor device. A well region (2) formed on a semiconductor substrate (1) includes a plurality of trench regions (12), and a source electrode (10) is connected to a source region (6) formed on a substrate surface between the trench regions (12). Adjacently to the source region (6), a high concentration region (11) is formed, which is brought into butting contact with the source electrode (10) together with the source region (6), whereby a substrate potential is fixed. A drain region (5) is formed at a bottom portion of the trench region (12), whose potential is taken to the substrate surface by a drain electrode (9) buried inside the trench region (12). An arbitrary voltage is applied to a gate electrode (4a, 4b), and the drain electrode (9), whereby carriers flow from the source region (6) to the drain region (5) and the semiconductor device is in an on-state.

Abstract: In a well region, an irregular structure is formed in a gate width direction, and a gate electrode is formed in concave portions and on top surfaces of convex portions via an insulating film. Upper and lower source regions are formed on one side of the gate electrode in a gate length direction, and upper and lower drain regions are formed on the other side thereof. By thus forming the lower source and drain regions in the source and drain regions, current concentration occurring in an upper portion of a channel region, which is generated as the gate length becomes shorter, may be suppressed and a current may be allowed to flow uniformly in the entire channel region, and hence an effective gate width is made wider owing to the irregular structure formed in the well region. Accordingly, an on-resistance of a semiconductor device is reduced to enhance driving performance.

Abstract: Provided is a method of manufacturing a semiconductor device capable of providing a stable trench depth, including: forming, on a semiconductor substrate, a first film having a high etching selectivity with respect to the semiconductor substrate; forming, on the first film, a second film having a high etching selectivity with respect to the first film; etching a region of a part of the second film and the first film to expose a surface of the semiconductor substrate in the region; and etching the exposed surface of the semiconductor substrate to form a trench.

Abstract: A semiconductor device has a semiconductor substrate and a high-resistance first conductivity type well region disposed on the semiconductor substrate. A low-resistance second conductivity type source region and a low-resistance second conductivity type drain region are formed in the well region. The well region is formed with trenches having convex and concave portions and that are disposed parallel to a source-drain direction of the source and drain regions. A gate insulating film is disposed on surfaces of the convex and concave portions of the trenches. A gate electrode is disposed on the gate insulating film.

Abstract: Trench portions (10) are formed in a well (5) in order to provide unevenness in the well (5). A gate electrode (2) is formed via an insulating film (7) on the upper surface and inside of the trench portions (10). A source region (3) is formed on one side of the gate electrode (2) in a gate length direction while a drain region (4) on another side. Both of the source region (3) and the drain region (4) are formed down to near the bottom portion of the gate electrode (2). By deeply forming the source region (3) and the drain region (4), current uniformly flows through the whole trench portions (10), and the unevenness formed in the well (5) increase the effective gate width to decrease the on-resistance of a semiconductor device 1 and to enhance the drivability thereof.

Abstract: Provided is a semiconductor device capable of easily setting a holding voltage with a low trigger voltage by locally forming a P-type diffusion layer between N-type source and drain diffusion layers of an NMOS transistor having a conventional drain structure used as an electrostatic protective element of the semiconductor device.

Abstract: A semiconductor device has a semiconductor substrate and a trench region having at least one trench disposed on a surface of the semiconductor substrate and having a trench length, a trench width and a trench depth. A well region is disposed in the substrate and surrounds the trench region. A source region and a drain region are disposed above the well region and around respective inner walls of the trench. The source region and the drain region are disposed in confronting relation relative one another and have a conductivity type different from a conductivity type of the well region. A gate insulating film is disposed on the surface of the semiconductor substrate and on an inner base and the inner walls of the trench. A gate electrode is disposed on the gate insulating film. A length of the gate electrode is shorter than the trench length and equal to a distance between the source region and the drain region.

Abstract: Decrease in parasitic resistance caused by paste for adhering a semiconductor device to a lead frame or by a semiconductor substrate is disclosed. In a semiconductor device having a semiconductor substrate with an electrode formed on a rear surface thereof, an uneven structure is formed on the rear surface of the semiconductor substrate, and the rear surface electrode is formed and is adhered to a lead frame, thereby decreasing parasitic resistance and improving driving capability.

Abstract: Provided is a semiconductor device having a structure in which: a well region of a high resistance p-type semiconductor is disposed in a given depth from a surface of an n-type or p-type semiconductor substrate; a plurality of trenches extend from the surface of the well region to a certain depth; a gate insulating film is formed on a surface of a convex/concave portion on which the trenches are formed; a gate electrode is embedded into the trenches. The semiconductor device includes: a gate electrode film that is disposed on a substrate surface in contact with the gate electrode embedded into the trenches in the convexo-concave portion region except for a portion in the vicinity of both ends of the trenches; and a source region and a drain region that are two low resistance n-type semiconductor layers which are disposed shallower than the depth of the well region in the well region except for a lower portion of the gate electrode film.

Abstract: A lateral trench MOS transistor is provided in which trenches extending to the source and drain regions are disposed parallel to the gate length direction, agate oxide is disposed on the trenches, a well is disposed under the trench region and the source and drain regions by using oblique ion implantation, a gate electrode is disposed on the gate oxide, and source and drain regions are disposed on the same plane as a bottom surface of a concave portion of the trenches self-aligned to the gate electrode by using oblique ion implantation.

Abstract: In a metal-oxide semiconductor transistor in which a gate width per unit area can be increased through a method other than microfabrication, there is provided a high driving performance metal-oxide semiconductor transistor in which a single or a plurality of semiconductor devices and another circuit can be consolidated on one chip. The metal-oxide semiconductor transistor includes a plurality of linear concave portions that are arranged in a channel width direction.