Patents by Inventor Tomomitsu Risaki
Tomomitsu Risaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150162296Abstract: In order to inhibit a crack under a pad opening without increasing a chip size, a protective film (6) includes a pad opening (9) that exposes a part of a topmost layer metal film (3). The pad opening (9) is rectangular and square, and has an opening width of d0. A second metal film (2) has an opening under the pad opening (9). The opening is rectangular and square, and has an opening width of d4. A distance between an opening edge of the protective film (6) and an opening edge of the second metal film (2) is d3. The second metal film (2) has a rectangular donut shape, and protrudes to an inner side of the pad opening (9) by the distance d3.Type: ApplicationFiled: May 21, 2013Publication date: June 11, 2015Inventors: Tomomitsu Risaki, Shoji Nakanishi, Hitomi Sakurai, Koichi Shimazaki
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Patent number: 8803231Abstract: Trench portions (10) are formed in a well (5) in order to provide unevenness in the well (5). A gate electrode (2) is formed via an insulating film (7) on the upper surface and inside of the trench portions (10). A source region (3) is formed on one side of the gate electrode (2) in a gate length direction while a drain region (4) on another side. Both of the source region (3) and the drain region (4) are formed down to near the bottom portion of the gate electrode (2). By deeply forming the source region (3) and the drain region (4), current uniformly flows through the whole trench portions (10), and the unevenness formed in the well (5) increases the effective gate width to decrease the on-resistance of a semiconductor device 1 and to enhance the drivability thereof.Type: GrantFiled: April 3, 2012Date of Patent: August 12, 2014Assignee: Seiko Instruments, Inc.Inventors: Tomomitsu Risaki, Jun Osanai
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Publication number: 20140217510Abstract: Provided is a semiconductor device which uses a comb-like N-type MOS transistor as an ESD protection element and is capable of uniformly operating the entire comb-like N-type MOS transistor. By adjusting a length L of a gate electrode of the N-type MOS transistor used as the ESD protection element in accordance with the distance from a contact for fixing a substrate potential, which is provided on a guard ring around an outer periphery, respective portion of N-type MOS transistor represented as a comb teeth uniformly enter snap-back operation, permitting avoidance of local concentration of current and obtainment of a desired ESD tolerance.Type: ApplicationFiled: January 29, 2014Publication date: August 7, 2014Applicant: SEIKO INSTRUMENTS INC.Inventors: Takeshi KOYAMA, Tomomitsu RISAKI
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Patent number: 8618606Abstract: Provided is a semiconductor device comprising: a PW layer formed at a surface of a semiconductor substrate; an NW layer formed at the surface of the semiconductor substrate to be in contact with the PW layer; a p+ base layer formed at the surface of the semiconductor substrate in the PW layer; an n+ collector layer formed at the surface of the semiconductor substrate in the NW layer; an n+ emitter layer located between the p+ base layer and the n+ collector layer and formed at the surface of the semiconductor substrate in the PW layer; and an n± layer formed between the n+ collector layer and the PW layer to be in contact with the n+ collector layer.Type: GrantFiled: November 1, 2012Date of Patent: December 31, 2013Assignee: Seiko Instruments Inc.Inventors: Tomomitsu Risaki, Shoji Nakanishi, Koichi Shimazaki
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Publication number: 20130277792Abstract: A semiconductor device having a clamp diode includes: a breakdown voltage adjusting first conductivity type low concentration region (5) provided on a semiconductor substrate (6); a second conductivity type high concentration region (1) provided within the breakdown voltage adjusting first conductivity type low concentration region (5), the second conductivity type high concentration region being circular; an element isolation insulating film (2) provided within the breakdown voltage adjusting first conductivity type low concentration region (5), the element isolation insulating film being provided in a ring shape and surrounding the second conductivity type high concentration region (1) without being held in contact therewith; and a first conductivity type high concentration region (3) provided outside the ring of the element isolation insulating film (2) within the breakdown voltage adjusting first conductivity type low concentration region (5).Type: ApplicationFiled: April 3, 2013Publication date: October 24, 2013Inventor: Tomomitsu RISAKI
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Patent number: 8390061Abstract: A semiconductor device has a well region formed of a first conductivity type semiconductor at a predetermined depth from a surface of a substrate, trenches formed in the well region, and a gate insulating film formed on surfaces of concave and convex portions of the trenches. A first gate electrode is embedded inside the trenches, and a second gate electrode is formed on the substrate in contact with the first gate electrode in regions of the concave and convex portions excluding vicinities of both ends of the trenches. Source and drain regions of a second conductivity type are formed from a part of a surface of the semiconductor so as to extend deeper in a side surface of the concave portion of each trench than in the surface of the convex portion of each trench and shallower than the depth of the well region.Type: GrantFiled: August 20, 2008Date of Patent: March 5, 2013Assignee: Seiko Instruments Inc.Inventor: Tomomitsu Risaki
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Patent number: 8324687Abstract: Provided is a semiconductor device comprising: a PW layer formed at a surface of a semiconductor substrate; an NW layer formed at the surface of the semiconductor substrate to be in contact with the PW layer; a p+ base layer formed at the surface of the semiconductor substrate in the PW layer; an n+ collector layer formed at the surface of the semiconductor substrate in the NW layer; an n+ emitter layer located between the p+ base layer and the n+ collector layer and formed at the surface of the semiconductor substrate in the PW layer; and an n± layer formed between the n+ collector layer and the PW layer to be in contact with the n+ collector layer.Type: GrantFiled: January 28, 2010Date of Patent: December 4, 2012Assignee: Seiko Instruments Inc.Inventors: Tomomitsu Risaki, Shoji Nakanishi, Koichi Shimazaki
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Publication number: 20120187476Abstract: Trench portions (10) are formed in a well (5) in order to provide unevenness in the well (5). A gate electrode (2) is formed via an insulating film (7) on the upper surface and inside of the trench portions (10). A source region (3) is formed on one side of the gate electrode (2) in a gate length direction while a drain region (4) on another side. Both of the source region (3) and the drain region (4) are formed down to near the bottom portion of the gate electrode (2). By deeply forming the source region (3) and the drain region (4), current uniformly flows through the whole trench portions (10), and the unevenness formed in the well (5) increase the effective gate width to decrease the on-resistance of a semiconductor device 1 and to enhance the drivability thereof.Type: ApplicationFiled: April 3, 2012Publication date: July 26, 2012Applicant: Seiko Instruments, Inc.Inventors: Tomomitsu Risaki, Jun Osanai
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Patent number: 8207575Abstract: In a well region, an irregular structure is formed in a gate width direction, and a gate electrode is formed in concave portions and on top surfaces of convex portions via an insulating film. Upper and lower source regions are formed on one side of the gate electrode in a gate length direction, and upper and lower drain regions are formed on the other side thereof. By thus forming the lower source and drain regions in the source and drain regions, current concentration occurring in an upper portion of a channel region, which is generated as the gate length becomes shorter, may be suppressed and a current may be allowed to flow uniformly in the entire channel region, and hence an effective gate width is made wider owing to the irregular structure formed in the well region. Accordingly, an on-resistance of a semiconductor device is reduced to enhance driving performance.Type: GrantFiled: January 3, 2011Date of Patent: June 26, 2012Assignee: Seiko Instruments Inc.Inventors: Tomomitsu Risaki, Yuichiro Kitajima
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Patent number: 8193060Abstract: Provided is a method for manufacturing a semiconductor device. A well region formed on a semiconductor substrate includes a plurality of trench regions, and a source electrode is connected to a source region formed on a substrate surface between the trench regions. Adjacently to the source region, a high concentration region is formed, which is brought into butting contact with the source electrode together with the source region, whereby a substrate potential is fixed. A drain region is formed at a bottom portion of the trench region, whose potential is taken to the substrate surface by a drain electrode buried inside the trench region. An arbitrary voltage is applied to a gate electrode, and the drain electrode, whereby carriers flow from the source region to the drain region and the semiconductor device is in an on-state.Type: GrantFiled: November 18, 2010Date of Patent: June 5, 2012Assignee: Seiko Instruments Inc.Inventor: Tomomitsu Risaki
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Patent number: 8168494Abstract: Trench portions (10) are formed in a well (5) in order to provide unevenness in the well (5). A gate electrode (2) is formed via an insulating film (7) on the upper surface and inside of the trench portions (10). A source region (3) is formed on one side of the gate electrode (2) in a gate length direction while a drain region (4) on another side. Both of the source region (3) and the drain region (4) are formed down to near the bottom portion of the gate electrode (2). By deeply forming the source region (3) and the drain region (4), current uniformly flows through the whole trench portions (10), and the unevenness formed in the well (5) increase the effective gate width to decrease the on-resistance of a semiconductor device 1 and to enhance the drivability thereof.Type: GrantFiled: February 7, 2008Date of Patent: May 1, 2012Assignee: Seiko Instruments Inc.Inventors: Tomomitsu Risaki, Jun Osanai
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Patent number: 8071460Abstract: In a method of manufacturing a semiconductor device, a first film is formed directly on a semiconductor substrate and a second film is formed on the first film. A region of the second film is then etched to form an opening that exposes the first film. The first film is then arbitrarily patterned by etching to expose a surface of the semiconductor substrate. Thereafter, the second film and the exposed surface of the semiconductor substrate are simultaneously etched using the patterned first film as a mask and in an etching ambient having a low etching rate for the first film and having a high etching rate for the second film and the semiconductor substrate until the second film is almost completely etched and a detection amount of a monitored element of the first film increases.Type: GrantFiled: December 4, 2008Date of Patent: December 6, 2011Assignee: Seiko Instruments Inc.Inventors: Tomomitsu Risaki, Jun Osanai
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Publication number: 20110221043Abstract: Provided is a semiconductor device suitable for preventing film peeling due to dicing and preventing abnormal discharge. The semiconductor device includes a scribe region (003) and an IC region (004). At least one separation groove (007) is provide in an inter-layer insulating film (002) in the scribe region 003, and a side wall (011) made of a plug metal film is formed on each lateral wall of the separation groove (007). A passivation film is provided to cover at least the side walls (011).Type: ApplicationFiled: February 28, 2011Publication date: September 15, 2011Inventors: Tomomitsu Risaki, Shoji Nakanishi, Koichi Shimazaki
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Publication number: 20110156138Abstract: In a well region, an irregular structure is formed in a gate width direction, and a gate electrode is formed in concave portions and on top surfaces of convex portions via an insulating film. Upper and lower source regions are formed on one side of the gate electrode in a gate length direction, and upper and lower drain regions are formed on the other side thereof. By thus forming the lower source and drain regions in the source and drain regions, current concentration occurring in an upper portion of a channel region, which is generated as the gate length becomes shorter, may be suppressed and a current may be allowed to flow uniformly in the entire channel region, and hence an effective gate width is made wider owing to the irregular structure formed in the well region. Accordingly, an on-resistance of a semiconductor device is reduced to enhance driving performance.Type: ApplicationFiled: January 3, 2011Publication date: June 30, 2011Inventors: Tomomitsu Risaki, Yuichiro Kitajima
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Publication number: 20110079847Abstract: Provided is a semiconductor device capable of easily setting a holding voltage with a low trigger voltage by locally forming a P-type diffusion layer between N-type source and drain diffusion layers of an NMOS transistor having a conventional drain structure used as an electrostatic protective element of the semiconductor device.Type: ApplicationFiled: December 7, 2010Publication date: April 7, 2011Inventors: Mika Ebihara, Tomomitsu Risaki
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Publication number: 20110065247Abstract: Provided is a method for manufacturing a semiconductor device. A well region formed on a semiconductor substrate includes a plurality of trench regions, and a source electrode is connected to a source region formed on a substrate surface between the trench regions. Adjacently to the source region, a high concentration region is formed, which is brought into butting contact with the source electrode together with the source region, whereby a substrate potential is fixed. A drain region is formed at a bottom portion of the trench region, whose potential is taken to the substrate surface by a drain electrode buried inside the trench region. An arbitrary voltage is applied to a gate electrode, and the drain electrode, whereby carriers flow from the source region to the drain region and the semiconductor device is in an on-state.Type: ApplicationFiled: November 18, 2010Publication date: March 17, 2011Inventor: Tomomitsu RISAKI
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Patent number: 7888212Abstract: In a well region, an irregular structure is formed in a gate width direction, and a gate electrode is formed in concave portions and on top surfaces of convex portions via an insulating film. Upper and lower source regions are formed on one side of the gate electrode in a gate length direction, and upper and lower drain regions are formed on the other side thereof. By thus forming the lower source and drain regions in the source and drain regions, current concentration occurring in an upper portion of a channel region, which is generated as the gate length becomes shorter, may be suppressed and a current may be allowed to flow uniformly in the entire channel region, and hence an effective gate width is made wider owing to the irregular structure formed in the well region. Accordingly, an on-resistance of a semiconductor device is reduced to enhance driving performance.Type: GrantFiled: February 25, 2009Date of Patent: February 15, 2011Assignee: Seiko Instruments Inc.Inventors: Tomomitsu Risaki, Yuichiro Kitajima
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Patent number: 7859049Abstract: Provided is a semiconductor device. A well region (2) formed on a semiconductor substrate (1) includes a plurality of trench regions (12), and a source electrode (10) is connected to a source region (6) formed on a substrate surface between the trench regions (12). Adjacently to the source region (6), a high concentration region (11) is formed, which is brought into butting contact with the source electrode (10) together with the source region (6), whereby a substrate potential is fixed. A drain region (5) is formed at a bottom portion of the trench region (12), whose potential is taken to the substrate surface by a drain electrode (9) buried inside the trench region (12). An arbitrary voltage is applied to a gate electrode (4a, 4b), and the drain electrode (9), whereby carriers flow from the source region (6) to the drain region (5) and the semiconductor device is in an on-state.Type: GrantFiled: February 25, 2009Date of Patent: December 28, 2010Assignee: Seiko Instruments Inc.Inventor: Tomomitsu Risaki
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Publication number: 20100289078Abstract: In order to further improve a driving performance without increasing an element area in a lateral MOS having a high driving performance, in which a gate width is increased per unit area by forming a plurality of trenches horizontally with respect to a gate length direction, the semiconductor device includes: a well region which is formed of a high resistance first conductivity type semiconductor at a predetermined depth from a surface of a semiconductor substrate; a plurality of trenches which extend from a surface to a midway depth in the well region; a gate insulating film which is formed on surfaces of concave and convex portions formed by the trenches; a gate electrode embedded inside the trenches; a gate electrode film which is formed on the surface of the substrate in contact with the gate electrode embedded inside the trenches in regions of the concave and convex portions, the regions excluding vicinities of both ends of the trenches; another gate electrode film which is embedded inside the trenches inType: ApplicationFiled: August 20, 2008Publication date: November 18, 2010Inventor: Tomomitsu Risaki
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Patent number: 7768102Abstract: A semiconductor device comprises a semiconductor chip having a rear surface provided with an uneven structure having a preselected pattern and comprised of concave and convex portions. The preselected pattern of the uneven structure is tilted so as to be in parallel to a crystal orientation of <110> of the semiconductor chip. An electrode is disposed on the concave and convex portions of the uneven structure.Type: GrantFiled: April 14, 2006Date of Patent: August 3, 2010Assignee: Seiko Instruments Inc.Inventor: Tomomitsu Risaki