Patents by Inventor Tomoyuki Yamazaki

Tomoyuki Yamazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6828645
    Abstract: A semiconductor device comprising: a semiconductor substrate, a dielectric film formed on the semiconductor substrate, a first electrode and a second electrode separated from each other on the dielectric film; a spiral thin film layer having both ends connected to the first electrode and the second electrode, respectively, the spiral thin film layer surrounding the first electrode, the thin film layer being formed on the dielectric layer, and a plurality of p-n diodes formed in series in the spiral thin film layer along a longitudinal direction of the spiral thin film layer.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: December 7, 2004
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Shinichi Jimbo, Jun Saito, Tomoyuki Yamazaki
  • Patent number: 6809393
    Abstract: A level shifter is provided that facilitates reducing high-bias-voltage application to a MOSFET and improving the reliability thereof. The level shifter includes an NMOSFET formed of a first isolated region in the surface portion of a P-type substrate, a source, a channel and a drain in the surface portion of a first isolated region, and a gate above the first isolated region; a second isolated region in the surface portion of P-type substrate and space apart from first isolated region; and high-potential portions including pinch resistance with a high breakdown voltage in second isolated region.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: October 26, 2004
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Tomoyuki Yamazaki
  • Publication number: 20030209774
    Abstract: A semiconductor device comprising: a semiconductor substrate, a dielectric film formed on the semiconductor substrate, a first electrode and a second electrode separated from each other on the dielectric film; a spiral thin film layer having both ends connected to the first electrode and the second electrode, respectively, the spiral thin film layer surrounding the first electrode, the thin film layer being formed on the dielectric layer, and a plurality of p-n diodes formed in series in the spiral thin film layer along a longitudinal direction of the spiral thin film layer.
    Type: Application
    Filed: June 12, 2003
    Publication date: November 13, 2003
    Inventors: Shinichi Jimbo, Jun Saito, Tomoyuki Yamazaki
  • Patent number: 6603185
    Abstract: A semiconductor device comprising: a semiconductor substrate, a dielectric film formed on the semiconductor substrate, a first electrode and a second electrode separated from each other on the dielectric film; a spiral thin film layer having both ends connected to the first electrode and the second electrode, respectively, the spiral thin film layer surrounding the first electrode, the thin film layer being formed on the dielectric layer, and a plurality of p-n diodes formed in series in the spiral thin film layer along a longitudinal direction of the spiral thin film layer.
    Type: Grant
    Filed: January 31, 2000
    Date of Patent: August 5, 2003
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Shinichi Jimbo, Jun Saito, Tomoyuki Yamazaki
  • Patent number: 5559355
    Abstract: Mutual interference is reduced between a main cell portion and a sensing cell portion for detecting the current flowing through the main cell portion of a vertical MOS semiconductor device, and accuracy and reliability of overcurrent detection are improved. In the device, well regions of (p) type are formed between the main and sensing cell portions for capturing the minority carriers. Breakdown of the gate oxide film caused by an open emitter electrode of the sensing cell portion is prevented by forming the (p) type well regions with ring shapes, by spacing the (p) type well regions by 5 to 20 .mu.m, and by adjusting the isolation withstand voltage between the main and sensing cell portions below the withstand voltage of the gate oxide film. A voltage spike is minimized by narrowing the overlap of the detecting and gate electrodes for reduced capacitance between these electrodes.
    Type: Grant
    Filed: June 20, 1995
    Date of Patent: September 24, 1996
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Tomoyuki Yamazaki, Shigeyuki Obinata, Masahito Otsuki, Seiji Momota, Tatsuhiko Fujihira
  • Patent number: 5559347
    Abstract: An insulated gate-type bipolar transistor with an overcurrent limiting function that is capable of keeping the ratio of a main current to a detection current constant even under different operating conditions, and capable of suppressing the voltage dependence of the limited-current value to perform stable overcurrent protection. P-wells are formed so that they are incorporated between main cell IGBTs as sensing cells for current detection on part of the semiconductor substrate on which a large number of main cells are formed integratedly, and current-detecting emitter electrodes connected to the P-wells are connected to an overcurrent-protection circuit and separated from the main emitter electrodes connected to the main IGBT cells.
    Type: Grant
    Filed: March 1, 1995
    Date of Patent: September 24, 1996
    Assignee: Fuji Electronic Co., Ltd.
    Inventors: Tomoyuki Yamazaki, Masahito Otsuki
  • Patent number: 5557128
    Abstract: For stabilized overcurrent protection, an insulated-gate type bipolar transistor (IGBT) is provided with an overcurrent limiting feature having reduced dependence of the limited-current value on the power supply voltage. Sensing cells 9 for current detection are formed on part of a semiconductor substrate 5 on which a large number of IGBT main cells 6 are formed integratedly. Emitter electrodes 10 of the sensing cells are connected to an external overcurrent-protection circuit for current detection and overcurrent protection. The sensing cells and the main cells are electrically separated. P-wells 11 for drawing out hole current, connected to the emitter electrodes of the main cells, are formed in a region along the circumference of the sensing cells so that interference between the carriers of the main cells and those of the sensing cells is suppressed and current ratio is stabilized.
    Type: Grant
    Filed: March 1, 1995
    Date of Patent: September 17, 1996
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Tomoyuki Yamazaki, Shigeyuki Obinata
  • Patent number: 5430323
    Abstract: An injection control-type Schottky barrier rectifier, including: a semiconductor region having a first conductivity type; a first diffusion region, which is formed in the semiconductor region and which has a second conductivity type, the second conductivity type being different from the first conductivity type, for forming a depletion layer in the semiconductor region when a turn-off voltage is applied to the Schottky barrier rectifier; a second diffusion region, which is formed in the semiconductor region and which has the second conductivity type, for causing conductivity modulation in the semiconductor region when a turn-on voltage is applied to the Schottky barrier rectifier; a barrier electrode which is ohmically connected with the first diffusion region and which forms a Schottky junction with the surface of the semiconductor region which is opposite to the second diffusion region with respect to the first diffusion region; a gate insulator film formed on the surface of the semiconductor region between
    Type: Grant
    Filed: September 30, 1993
    Date of Patent: July 4, 1995
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Tomoyuki Yamazaki, Naoki Kumagai