Abstract: A random number generator and a random number generating method thereof are provided. The random number generator includes a signal generating unit and a sampling unit. The signal generating unit is adapted for memorizing a status of a noise generated during a transient of an output signal of an output buffer, and accordingly generating a frequency conversion signal which changes according to time and ambient factors. The sampling unit is coupled to the signal generating unit for receiving the frequency conversion signal, and sampling the frequency conversion signal according to a sampling clock pulse, so as to obtain a plurality of sets of unpredictable random number codes.

Abstract: A converter circuit is provided herein. In the converter, a voltage converting unit receives an input voltage and outputs an output voltage according to the magnitude of the input voltage by switching operation based on a control clock signal. A comparing circuit generates a power good pulse signal by comparing the output voltage with a reference voltage. A pulse width frequency modulation circuit receives the power good pulse signal and a source clock signal to provide the control clock signal. The pulse width of the source clock signal is varied gradually and the frequency of the source clock signal is also changed during a period that the power good pulse signal remains in the first logic state, and the pulse width frequency modulated source clock signal is output as the control clock signal.

Abstract: A programmable detection adjuster is disclosed. The programmable detection adjuster comprises a bandgap and an adjusting circuit. The bandgap comprises a power input terminal, a voltage output terminal, a main resistance and a plurality of resistors. The adjusting circuit comprises a plurality of adjusting resistors, a plurality of transistor switches, a logic controller and detection circuits; said adjusting resistors connected to the main resistance of the bandgap in series. The adjusting resistors are respectively connected to the transistor switch in parallel. The transistor switches are connected to the logic controller. The logic controller is respectively connected to the detection circuits. The detection circuit detects the corresponding resistances in the detection circuit and outputs a voltage level to the logic controller to enable the logic controller to control a conduction of the transistor switches according to a logic conversion table.

Abstract: A method of forming a continuous layer of film, the method comprising providing a substrate having a surface, forming a first patterned layer of film on the surface, the first patterned layer of film including a plurality of first film units separated from each other, and forming a second patterned layer of film over the first patterned layer of film, the second patterned layer of film extending along the first patterned layer of film and including a plurality of second film units separated from each other, each of the plurality of second film units connecting at least two immediately adjacent first film units of the first patterned layer of film

Abstract: A thin-film transistor and fabrication method thereof are provided. A controlled micro-line is formed by inkjet printing in combination with the coffee ring effect. At least two organic thin-film transistors are formed on two ring ridges of the coffee rings. For example, N-type and P-type soluble semiconductor materials may be formed on two adjacent ring ridges to form a complementary metal-oxide semiconductor (CMOS) device. Thus, the invention can simplify the process for fabricating thin-film transistors and increase their applications.

Abstract: A programmable detection adjuster is disclosed. The programmable detection adjuster comprises a bandgap and an adjusting circuit. The bandgap comprises a power input terminal, a voltage output terminal, a main resistance and a plurality of resistors. The adjusting circuit comprises a plurality of adjusting resistors, a plurality of transistor switches, a logic controller and detection circuits; said adjusting resistors connected to the main resistance of the bandgap in series. The adjusting resistors are respectively connected to the transistor switch in parallel. The transistor switches are connected to the logic controller. The logic controller is respectively connected to the detection circuits. The detection circuit detects the corresponding resistances in the detection circuit and outputs a voltage level to the logic controller to enable the logic controller to control a conduction of the transistor switches according to a logic conversion table.

Abstract: A dental attachment including a magnet element delivering a magnetic attraction force, a yoke of a soft magnetic material and including a recess for housing the magnet element, and a disc joined to the yoke so as to close the opening of the recess with the magnet element housed in the recess. The yoke has a substantially disc shape portion and collars protruding axially outwardly from the outer peripheral surface of the disc shape portion. The collars are formed to be separated in at least two locations in a substantially peripheral direction, and non-protruding portions having radially outward projection amounts from zero to 50% of the maximum projection amount at the collars are provided between respective collars.

Abstract: A method of fabricating a color organic electroluminescent display involves forming cathode electrodes on a substrate, and forming a first organic semiconductor layer having an electron-injection transporting property on the cathode electrodes. Solutions containing organic light-emitting material that can dissolve portions of the first organic semiconductor layer are patterned on the first organic semiconductor layer. Then, a solvent in the solutions is removed to form regions having second organic semiconductor layers and mixed organic semiconductor layers, wherein the second organic semiconductor layers are formed on the first organic semiconductor layer and are mostly composed of the organic light-emitting material, and the mixed organic semiconductor layers, composed of the organic light-emitting material and material constituting the first organic semiconductor layer, are embedded in the first organic semiconductor layer. Anode electrodes are formed over the first and second organic semiconductor layers.

Abstract: A polymeric light emitting diode (PLED) device comprises: a substrate; a positive electrode formed above the substrate; a hole transportation layer formed above the positive electrode; an organic light emitting composite layer formed above the hole transportation layer, comprising a plurality of organic light emitting layers, wherein every organic light emitting layer has an polymeric host material with a higher energy gap, and at least one of the organic light emitting layers is doped with an polymeric material with a lower energy gap; and a negative electrode formed above the organic light emitting composite layer.

Abstract: A voltage detection circuit for detecting the voltage level of a first power source. A first transistor includes a first gate, a first source, and a first drain coupled to the first gate. A second transistor includes a second gate, a second source, and a second drain coupled to the second gate. A comparator includes a first input terminal, a second input terminal coupled to the second drain, and an output terminal. A first resistor is coupled between the first input terminal and the first drain. A second resistor is coupled to the first power source. A third resistor is coupled between the second resistor and the first input terminal. A fourth resistor is coupled between the second resistor and input terminal. A fifth resistor is coupled between the first source, and a second power source. A resistive device is coupled between the first source, and the first power source.

Abstract: A voltage detection circuit for detecting the voltage level of a first power source. A first transistor includes a first gate, a first source, and a first drain coupled to the first gate. A second transistor includes a second gate, a second source, and a second drain coupled to the second gate. A comparator includes a first input terminal, a second input terminal coupled to the second drain, and an output terminal. A first resistor is coupled between the first input terminal and the first drain. A second resistor is coupled to the first power source. A third resistor is coupled between the second resistor and the first input terminal. A fourth resistor is coupled between the second resistor and input terminal. A fifth resistor is coupled between the first source, and a second power source. A resistive device is coupled between the first source, and the first power source.

Abstract: A voltage detection circuit for detecting the voltage level of a first power source. A first transistor includes a first gate, a first source, and a first drain coupled to the first gate. A second transistor includes a second gate, a second source, and a second drain coupled to the second gate. A comparator includes a first input terminal, a second input terminal coupled to the second drain, and an output terminal. A first resistor is coupled between the first input terminal and the first drain. A second resistor is coupled to the first power source. A third resistor is coupled between the second resistor and the first input terminal. A fourth resistor is coupled between the second resistor and input terminal. A fifth resistor is coupled between the first source, and a second power source. A resistive device is coupled between the first source, and the first power source.

Abstract: A voltage detection circuit for detecting the voltage level of a first power source. A first transistor includes a first gate, a first source, and a first drain coupled to the first gate. A second transistor includes a second gate, a second source, and a second drain coupled to the second gate. A comparator includes a first input terminal, a second input terminal coupled to the second drain, and an output terminal. A first resistor is coupled between the first input terminal and the first drain. A second resistor is coupled to the first power source. A third resistor is coupled between the second resistor and the first input terminal. A fourth resistor is coupled between the second resistor and input terminal. A fifth resistor is coupled between the first source, and a second power source. A resistive device is coupled between the first source, and the first power source.

Abstract: An active matrix LED display driving circuit. The circuit comprises a first transistor having a drain, a source coupled to receive a data signal and a gate coupled to receive a scan signal and, a second transistor having a drain, a source coupled to receive the data signal and a gate coupled to receive the scan signal, a third transistor having a source, a drain coupled to the drain of the second transistor and a gate coupled to the drain of the first transistor, a fourth transistor having a drain coupled to receive a first voltage, and a gate coupled to receive the scan signal and a source coupled to the drain of the second transistor, a light emitting diode having an anode coupled to the source of the third transistor and a cathode coupled to receive a second voltage, and a capacitor coupled between the gate and source of the third transistor.

Abstract: A fast start up oscillator. The fast start-up oscillator includes a power-on-reset detect circuit, a bandgap circuit, a voltage detect circuit, a RC-oscillator, and a count two circuit. The fast start-up oscillator is provided with a fast stabilized voltage source to ensure oscillation accurate and quickly such that the system is woken up.

Abstract: An active matrix LED display driving circuit. The circuit comprises a first transistor having a drain, a source coupled to receive a data signal and a gate coupled to receive a scan signal and, a second transistor having a drain, a source coupled to receive the data signal and a gate coupled to receive the scan signal, a third transistor having a source, a drain coupled to the drain of the second transistor and a gate coupled to the drain of the first transistor, a fourth transistor having a drain coupled to receive a first voltage, and a gate coupled to receive the scan signal and a source coupled to the drain of the second transistor, a light emitting diode having an anode coupled to the source of the third transistor and a cathode coupled to receive a second voltage, and a capacitor coupled between the gate and source of the third transistor.

Abstract: A fast start up oscillator. The fast start-up oscillator includes a power-on-reset detect circuit, a bandgap circuit, a voltage detect circuit, a RC-oscillator, and a count two circuit. The fast start-up oscillator is provided with a fast stabilized voltage source to ensure oscillation accurate and quickly such that the system is woken up.

Abstract: A power on detect circuit. The power on detect circuit is designed for detecting low power on voltage and having low temperature coefficient of power on voltage. Detected power on voltage range is insensitive to process and temperature. The power on detect circuit includes two MOS transistors, one has a larger aspect ratio and is coupled to a voltage source by two series resistors, the first resistor and the second resistor, and the other has a lower aspect ratio and is coupled to the voltage source by a resistor, the third resistor. A comparator senses out voltage difference the first resistor and the third resistor to generate a power on reset signal.

Abstract: A method comprising receiving media content and analyzing one or more attributes of successive shots of the received media. Based, at least in part on the analysis of the one or more attributes, generating a correlation score for each of the successive shots, wherein scene segmentation is performed to group semantically cohesive shots.

Abstract: A voltage-averaged temperature compensation method at start-up. The method implements two pluralities of PMOS devices such that a respective voltage-averaged temperature compensation circuit produces a first temperature voltage and a second temperature voltage to compensate temperature effect and accordingly produces an output voltage having a damping waveform in lower region when activating the first plurality of PMOS devices and a desired waveform in upper region when activating the second plurality of PMOS devices. As such, the error reference or control due to a prior damping waveform is eliminated.