Patents by Inventor Tong-Yu Chen

Tong-Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10847412
    Abstract: A method for manufacturing an interconnect structure with air gaps includes the following steps. A substrate including a first insulating layer formed thereon is provided. Plural conductive lines are formed in the first insulating layer. A patterned hard mask is formed on the first insulating layer and the conductive lines and exposes portions of the first insulating layer and portions of the conductive lines. The exposed portions of the first insulating layer are then removed to form a plurality of recesses in the first insulating layer. After that, a second insulating layer and a third insulating layer are formed in the recesses to seal the recesses and to form a plurality of air gaps in the recesses. At least two air gaps are respectively formed at two sides of one conductive line of the plurality of conductive lines. A via structure is then formed on the one conductive line.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: November 24, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tong-Yu Chen, Chia-Fang Lin
  • Patent number: 10658232
    Abstract: An interconnect layout structure, having a plurality of air gaps, includes a substrate having an insulating material disposed thereon and a conductive line disposed in the insulating material and extending along a first direction. The air gaps are formed in the insulating material and are arranged end-to-end along the first direction and immediately adjacent to a same side of the conductive line. A patterned hard mask is disposed on the conductive line and has a sidewall extending along a second direction that is perpendicular to the first direction and passing between the adjacent air gaps from the top view. A via structure is formed on the conductive line and is electrically connected to the conductive line.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: May 19, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tong-Yu Chen, Chia-Fang Lin
  • Publication number: 20190367632
    Abstract: Disclosed herein are humanized antibodies, antigen-binding fragments thereof, and antibody conjugates, that are capable of specifically binding to certain biantennary Lewis antigens, which antigens are expressed in a variety of cancers. The presently disclosed antibodies are useful to target antigen-expressing cells for treatment or detection of disease, including various cancers. Also provided are polynucleotides, vectors, and host cells for producing the disclosed antibodies and antigen-binding fragments thereof. Pharmaceutical compositions, methods of treatment and detection, and uses of the antibodies, antigen-binding fragments, antibody conjugates, and compositions are also provided.
    Type: Application
    Filed: May 30, 2019
    Publication date: December 5, 2019
    Inventors: Tong-Hsuan CHANG, Mei-Chun YANG, Liahng-Yirn LIU, Jerry TING, Shu-Yen CHANG, Yen-Ying CHEN, Yu-Yu LIN, Shu-Lun TANG
  • Publication number: 20190214292
    Abstract: A method for manufacturing an interconnect structure with air gaps includes the following steps. A substrate including a first insulating layer formed thereon is provided. Plural conductive lines are formed in the first insulating layer. A patterned hard mask is formed on the first insulating layer and the conductive lines and exposes portions of the first insulating layer and portions of the conductive lines. The exposed portions of the first insulating layer are then removed to form a plurality of recesses in the first insulating layer. After that, a second insulating layer and a third insulating layer are formed in the recesses to seal the recesses and to form a plurality of air gaps in the recesses. At least two air gaps are respectively formed at two sides of one conductive line of the plurality of conductive lines. A via structure is then formed on the one conductive line.
    Type: Application
    Filed: March 14, 2019
    Publication date: July 11, 2019
    Inventors: Tong-Yu Chen, Chia-Fang Lin
  • Patent number: 10276429
    Abstract: An interconnect layout structure having air gaps includes a plurality of air gaps extended along a direction, and at least a first interconnect unit disposed in between the air gaps. The first interconnect unit includes a first conductive line, a first landing mark situated on the first conductive line and a first via structure situated on the first landing mark. The first via structure penetrates the first landing mark and is electrically connected to the first conductive line. And the first landing mark physically separates the air gaps arranged in a straight line.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: April 30, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tong-Yu Chen, Chia-Fang Lin
  • Publication number: 20180366364
    Abstract: An interconnect layout structure, having a plurality of air gaps, includes a substrate having an insulating material disposed thereon and a conductive line disposed in the insulating material and extending along a first direction. The air gaps are formed in the insulating material and are arranged end-to-end along the first direction and immediately adjacent to a same side of the conductive line. A patterned hard mask is disposed on the conductive line and has a sidewall extending along a second direction that is perpendicular to the first direction and passing between the adjacent air gaps from the top view. A via structure is formed on the conductive line and is electrically connected to the conductive line.
    Type: Application
    Filed: August 22, 2018
    Publication date: December 20, 2018
    Inventors: Tong-Yu Chen, Chia-Fang Lin
  • Patent number: 10134449
    Abstract: A semiconductor memory device including a memory cell having a plurality of memory cells, a first P-type well region, a second P-type well region, and an N-type well region disposed between the first P-Type well region and the second P-type well region. The semiconductor memory element defines a plurality of first regions and a plurality of second regions, each of the first regions and each of the second regions including one of the memory cells, each of the second regions further includes at least two first voltage providing contacts, and at least one second voltage providing contact, wherein the first voltage providing contacts and the second voltage providing contact are not located within each first region.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: November 20, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Hung Chen, Meng-Ping Chuang, Tong-Yu Chen, Yu-Tse Kuo
  • Publication number: 20180286474
    Abstract: A semiconductor memory device including a memory cell having a plurality of memory cells, a first P-type well region, a second P-type well region, and an N-type well region disposed between the first P-Type well region and the second P-type well region. The semiconductor memory element defines a plurality of first regions and a plurality of second regions, each of the first regions and each of the second regions including one of the memory cells, each of the second regions further includes at least two first voltage providing contacts, and at least one second voltage providing contact, wherein the first voltage providing contacts and the second voltage providing contact are not located within each first region.
    Type: Application
    Filed: May 8, 2017
    Publication date: October 4, 2018
    Inventors: Chien-Hung Chen, Meng-Ping Chuang, Tong-Yu Chen, Yu-Tse Kuo
  • Patent number: 9871123
    Abstract: A field effect transistor (FET) and a manufacturing method thereof are provided. The FET includes a substrate, a fin bump, an insulating layer, a charge trapping structure and a gate structure. The fin bump is disposed on the substrate. The insulating layer is disposed on the substrate and located at two sides of the fin bump. The charge trapping structure is disposed on the insulating layer and located at least one side of the fin bump. A cross-section of the charge trapping structure is L-shaped. The gate structure covers the fin bump and the charge trapping structure.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: January 16, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tong-Yu Chen, Chih-Jung Wang
  • Publication number: 20170194191
    Abstract: An interconnect layout structure having air gaps includes a plurality of air gaps extended along a direction, and at least a first interconnect unit disposed in between the air gaps. The first interconnect unit includes a first conductive line, a first landing mark situated on the first conductive line and a first via structure situated on the first landing mark. The first via structure penetrates the first landing mark and is electrically connected to the first conductive line. And the first landing mark physically separates the air gaps arranged in a straight line.
    Type: Application
    Filed: January 27, 2016
    Publication date: July 6, 2017
    Inventors: Tong-Yu Chen, Chia-Fang Lin
  • Patent number: 9378998
    Abstract: A method of forming a harmonic-effect-suppression structure is disclosed. The method includes: providing a semiconductor substrate having a base semiconductor substrate, a buried dielectric on the base semiconductor substrate, and a surface semiconductor layer on the buried dielectric. Next, a deep trench is formed extending through the surface semiconductor layer and the buried dielectric into the base semiconductor substrate, a silicon layer is formed within a lower portion of the deep trench, the silicon layer allowed to have a top surface height substantially the same as or lower than a top surface height of the base semiconductor substrate, and a dielectric layer is formed within the deep trench and on the silicon layer.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: June 28, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tong-Yu Chen, Kuo-Yuh Yang
  • Patent number: 9214384
    Abstract: The present invention provides a method of forming a trench in a semiconductor substrate. First, a first patterned mask layer is formed on a semiconductor substrate. The first patterned mask layer has a first trench. Then, a material layer is formed along the first trench. Then, a second patterned mask layer is formed on the material layer to completely fill the first trench. A part of the material layer is removed when the portion of the material layer between the second patterned mask layer and the semiconductor substrate is maintained so as to form a second trench. Lastly, an etching process is performed by using the first patterned mask layer and the second patterned mask layer as a mask.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: December 15, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tong-Yu Chen, Chih-Jung Wang
  • Patent number: 9105590
    Abstract: A semiconductor structure is provided in the present invention. The semiconductor structure includes a substrate, a first material layer and a second material layer. A trench region is defined on the substrate. The trench region includes two separated first regions and a second region, wherein the second region is adjacent to and between the two first regions. The first material layer is disposed on the substrate outside the trench region. The second material layer is disposed in the second region and is level with the first material layer.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: August 11, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Tong-Yu Chen
  • Publication number: 20150221543
    Abstract: A method of forming a harmonic-effect-suppression structure is disclosed. The method includes: providing a semiconductor substrate having a base semiconductor substrate, a buried dielectric on the base semiconductor substrate, and a surface semiconductor layer on the buried dielectric. Next, a deep trench is formed extending through the surface semiconductor layer and the buried dielectric into the base semiconductor substrate, a silicon layer is formed within a lower portion of the deep trench, the silicon layer allowed to have a top surface height substantially the same as or lower than a top surface height of the base semiconductor substrate, and a dielectric layer is formed within the deep trench and on the silicon layer.
    Type: Application
    Filed: April 15, 2015
    Publication date: August 6, 2015
    Inventors: Tong-Yu Chen, Kuo-Yuh Yang
  • Publication number: 20150179652
    Abstract: A patterned structure of a semiconductor device includes a substrate, at least a first patterned structure, and at least a second patterned structure. The first patterned structure is a single-layered structure, and the second patterned structure is a multi-layered structure. The width of the second patterned structure is greater than the width of the first patterned structure.
    Type: Application
    Filed: March 5, 2015
    Publication date: June 25, 2015
    Inventors: Chih-Jung Wang, Tong-Yu Chen
  • Publication number: 20150171194
    Abstract: A field effect transistor (FET) and a manufacturing method thereof are provided. The FET includes a substrate, a fin bump, an insulating layer, a charge trapping structure and a gate structure. The fin bump is disposed on the substrate. The insulating layer is disposed on the substrate and located at two sides of the fin bump. The charge trapping structure is disposed on the insulating layer and located at at least one side of the fin bump. A cross-section of the charge trapping structure is L-shaped. The gate structure covers the fin bump and the charge trapping structure.
    Type: Application
    Filed: March 3, 2015
    Publication date: June 18, 2015
    Inventors: Tong-Yu Chen, Chih-Jung Wang
  • Patent number: 9048285
    Abstract: A semiconductor structure includes a SOI/BOX semiconductor substrate, a device, a deep trench, a silicon layer, and a dielectric layer. The deep trench is adjacent to the device and extends through a shallow trench isolation layer within the SOI layer and the BOX layer and into the base semiconductor substrate. The silicon layer is disposed within a lower portion of the deep trench. The silicon layer has a top surface height substantially the same as or lower than a top surface height of the base semiconductor substrate. The dielectric layer is disposed within the deep trench and on the silicon layer. The deep trench can be formed before or after formation of an interlayer dielectric.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: June 2, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tong-Yu Chen, Kuo-Yuh Yang
  • Publication number: 20150111385
    Abstract: The present invention provides a method of forming a trench in a semiconductor substrate. First, a first patterned mask layer is formed on a semiconductor substrate. The first patterned mask layer has a first trench. Then, a material layer is formed along the first trench. Then, a second patterned mask layer is formed on the material layer to completely fill the first trench. A part of the material layer is removed when the portion of the material layer between the second patterned mask layer and the semiconductor substrate is maintained so as to form a second trench. Lastly, an etching process is performed by using the first patterned mask layer and the second patterned mask layer as a mask.
    Type: Application
    Filed: December 24, 2014
    Publication date: April 23, 2015
    Inventors: Tong-Yu Chen, Chih-Jung Wang
  • Patent number: 9012975
    Abstract: A field effect transistor (FET) and a manufacturing method thereof are provided. The FET includes a substrate, a fin bump, an insulating layer, a charge trapping structure and a gate structure. The fin bump is disposed on the substrate. The insulating layer is disposed on the substrate and located at two sides of the fin bump. The charge trapping structure is disposed on the insulating layer and located at at least one side of the fin bump. A cross-section of the charge trapping structure is L-shaped. The gate structure covers the fin bump and the charge trapping structure.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: April 21, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Tong-Yu Chen, Chih-Jung Wang
  • Patent number: 9006107
    Abstract: A method for fabricating a patterned structure in a semiconductor device is provided. First, a substrate with a first region and a second region is provided. Then, a plurality of sacrificial patterns is respectively formed within the first region and the second region. A first spacer is then formed on the sidewalls of each of the sacrificial patterns followed by forming a mask layer to cover the sacrificial patterns located within the first region. Finally, the first spacer exposed from the mask layer is trimmed to be a second spacer and the mask layer is then removed.
    Type: Grant
    Filed: March 11, 2012
    Date of Patent: April 14, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Jung Wang, Tong-Yu Chen