Abstract: Application of an adhesion promoter to a cap layer and oxidation of the adhesion promoter prior to deposition of an organic interlevel dielectric thereon reduces via resistance problems during thermal cycles of semiconductor wafers embodying multiple levels of metal and organic interlevel dielectrics.

Abstract: A process for forming fusible links in an integrated circuit in which the fusible links are formed in the final metallization layer simultaneously with bonding pads. The process can be applied in the fabrication of integrated circuits that employ copper metallization and low k dielectric materials. After patterning the final metal (aluminum) layer to form the fusible links and the bonding pads, a dielectric etch stop layer is formed over the final metal layer before a passivation layer is deposited. The passivation layer is removed in areas over the fusible links and the bonding pads. The dielectric etch stop layer is removed either from above the bonding pads only, or from above both the bonding pads and the fusible links.

Abstract: A process for forming fusible links in an integrated circuit in which the fusible links are formed in the final metallization layer simultaneously with bonding pads. The process can be applied in the fabrication of integrated circuits that employ copper metallization and low k dielectric materials. After patterning the final metal (aluminum) layer to form the fusible links and the bonding pads, a dielectric etch stop layer is formed over the final metal layer before a passivation layer is deposited. The passivation layer is removed in areas over the fusible links and the bonding pads. The dielectric etch stop layer is removed either from above the bonding pads only, or from above both the bonding pads and the fusible links.

Abstract: Application of an adhesion promoter to a cap layer and oxidation of the adhesion promoter prior to deposition of an organic interlevel dielectric thereon reduces via resistance problems during thermal cycles of semiconductor wafers embodying multiple levels of metal and organic interlevel dielectrics.

Abstract: The invention is directed towards a method for forming openings in low-k dielectric layers. A cap layer, a low-k dielectric layer, a metal hard mask layer and a hard mask layer are formed in sequence on a provided substrate with metal wires. After patterning the metal hard mask layer and the hard mask layer to form a first opening, a fluid filling material layer is formed on the hard mask layer and fills the first opening. Using a patterned photoresist layer as a mask to define the filling material layer and the low-k dielectric layer, a second opening is obtained. After removing the photoresist layer along with the filling material layer, a damascene opening is formed by using the metal hard mask and the hard mask layers as a mask and the cap layer as an etching stop layer.

Abstract: A method for forming a damascene opening in a polymer-based dielectric layer is introduced. The method includes providing a substrate, which has also a conductive structure layer and a polymer-based dielectric layer formed thereon already. The polymer-based dielectric layer is uniformly hardened by a thermal treatment. A mask layer is formed on the polymer-based dielectric layer. The mask layer and the polymer-based dielectric layer are patterned to form an opening. The opening exposes a surface of the polymer-based dielectric layer. The exposed surface of the polymer-based dielectric layer is further hardened by a local hardening process. The local hardening process includes using an irradiation source of a high energy light beam, electron beam or ion beam to proceed the local hardening. The irradiation source can be incident onto the substrate by vertical angle or inclining angle. The substrate can also be rotated.

Abstract: The invention is directed towards a method for forming openings in low-k dielectric layers. A cap layer, a low-k dielectric layer, a metal hard mask layer and a hard mask layer are formed in sequence on a provided substrate with metal wires. After patterning the metal hard mask layer and the hard mask layer to form a first opening, a fluid filling material layer is formed on the hard mask layer and fills the first opening. Using a patterned photoresist layer as a mask to define the filling material layer and the low-k dielectric layer, a second opening is obtained. After removing the photoresist layer along with the filling material layer, a damascene opening is formed by using the metal hard mask and the hard mask layers as a mask and the cap layer as an etching stop layer.

Abstract: The invention is directed towards a method for forming openings in low-k dielectric layers and a structure for forming an opening thereof. A mask layer comprising at least one metal hard mask layer and one or more hard mask layers is applied on the dielectric layer for forming the opening.

Abstract: A method for forming a three dimensional semiconductor structure which has vertical capacitor(s) but not horizontal capacitor(s). The method essentially at least includes these steps of forming bottom plates within dielectric layers, forming another dielectric layer over bottom plates, removing all dielectric layers over bottom plates, forming optional liner(s) and capacitor dielectric layers on bottom plates, and forming top plates over capacitor dielectric layers. Note that shape of bottom plates is alike to the bottom connection and verticle fingers, also note that each gap within bottom plates is filled by both capacitor dielectric layer and top plate.

Abstract: A method of forming a dual damascene structure. A first dielectric layer, an etching stop layer, a second dielectric layer and a hard mask layer are sequentially formed over a substrate. Photolithographic and etching operations are conducted to remove a portion of the hard mask layer, the second dielectric layer, the etching stop layer and the first dielectric layer so that a via opening is formed. A conformal dielectric layer is formed on the surface of the hard mask layer and the interior surface of the via opening. An anisotropic etching operation is carried out to form spacers on the sidewalls of the via opening. A patterned photoresist layer is formed over the hard mask layer. Using the patterned photoresist layer as a mask, a portion of the second dielectric layer is removed to form a trench. The patterned photoresist layer is removed. Conductive material is deposited over the substrate to fill the via opening and the trench.

Abstract: A damascene process for forming a via that leads to a conductive layer on a substrate. A low dielectric constant material layer is formed over the substrate. A low temperature hard mask layer is formed over the low dielectric constant material layer. The low temperature hard mask layer is patterned to form an opening above the conductive layer. Using the low temperature hard mask layer as a mask, the exposed low dielectric constant material layer is etched to form a via hole. An adhesion promoter liner is formed on the interior walls of the via hole. Metallic material is deposited into the via hole to form a via.

Abstract: A method for forming a damascene opening in a polymer-based dielectric layer is introduced. The method includes providing a substrate, which has also a conductive structure layer and a polymer-based dielectric layer formed thereon already. The polymer-based dielectric layer is uniformly hardened by a thermal treatment. A mask layer is formed on the polymer-based dielectric layer. The mask layer and the polymer-based dielectric layer are patterned to form an opening. The opening exposes a surface of the polymer-based dielectric layer. The exposed surface of the polymer-based dielectric layer is further hardened by a local hardening process. The local hardening process includes using an irradiation source of a high energy light beam, electron beam or ion beam to proceed the local hardening. The irradiation source can be incident onto the substrate by vertical angle or inclining angle. The substrate can also be rotated.

Abstract: A substrate is provided. A first dielectric is formed over the substrate, and an etching stop layer and a second dielectric are formed in turn on the first dielectric by deposition. An anti-reflection layer is formed over the second dielectric. Then, a photo-resist layer is formed and defined over the anti-reflection layer. A gap-filling material is filled on the second dielectric and into the via hole. Subsequently, the gap-filling material is etched back and is turned on the end point and the long over etch is applied to make sure the photo-resist thickness is below middle stop layer. If the first dielectric reacts with the photo-resist plug in the via hole, the bottom anti-reflection coating or thin oxide are used as a barrier before the trench photo-resist is patterned. If the first dielectric does not react with the photo-resist plug in the via hole, the trench photo-resist is patterned directly. Then, the trench etch is performed.

Abstract: The present disclosure pertains to an integrated post-etch treatment method which is performed after a dielectric etch process. Using the method of the invention, byproducts formed on the sidewalls of contact vias during the dielectric etch process can be removed efficiently. The method of the invention also reduces or eliminates the problem of polymer accumulation on process chamber surfaces. An overlying photoresist layer and anti-reflection layer are removed during the performance of the post-etch treatment method. Typically, after the etch of a dielectric material to define pattern or interconnect filling spaces, a series of post-etch treatment steps is performed to remove residues remaining on the wafer after the dielectric etch process. According to the method of the present invention, a post-etch treatment method including one or more steps is performed after the dielectric etch process, preferably within the same processing chamber in which the dielectric etch process was performed.

Abstract: The present invention relates to a method of removing a photo-resist layer from a semiconductor wafer. The semiconductor wafer comprises an inter-metal dielectric layer (IMD), and a photo-resist layer positioned on the IMD. The method comprises performing a dry cleaning process by injecting a nitrogen-containing gas into an oxygen-free environment and utilizing a plasma reaction to remove most of the photo-resist layer, and performing a wet cleaning process to completely remove the photo-resist layer.

Abstract: A method of manufacturing metallic interconnects. A substrate has a copper line formed therein. An inter-metal dielectric layer is formed over the substrate and the copper line. A patterned photoresist layer is formed over the inter-metal dielectric layer. The inter-metal dielectric layer is etched to form a trench and a contact opening that exposes a portion of the copper line, wherein the contact opening is under the trench. At a low temperature and using a plasma derived from a gaseous mixture N2H2 (H2:4%)/O2, the photoresist layer is removed. Any copper oxide layer formed on the copper line in the process of removing photoresist material is reduced back to copper using gaseous N2H2 (H2:4%). A barrier layer conformal to the trench and the contact opening profile is formed. Copper is deposited to form a conformal first copper layer over the trench and the contact opening.

Abstract: A method of forming borderless contacts is provided. A substrate is provided. The substrate has at least a logic region and a memory region. A MOS transistor and a STI structure are formed on the logic region. The MOS transistor comprises a gate, a source/drain region and a cap insulating layer on the gate. An etching stop layer is formed on the substrate to cover the MSO transistor and the STI structure. A dielectric layer is formed in the etching stop layer. The dielectric layer, the etching stop layer and the cap insulating layer are partially removed to form a first opening according to the pattern of a first mask layer. The first opening exposes the gate. According to the pattern of a second mask layer, the dielectric layer and the etching stop layer are partially removed to form openings, which expose the source/drain region, in the dielectric layer.

Abstract: A metallization method for forming multilevel interconnect is disclosed. The method includes firstly providing a first conductor layer on which there is a dielectric layer. A glue layer is then formed on the dielectric layer, followed by forming an opening from top surface of the glue layer to the first conductor layer. After forming a barrier layer on the glue layer and all surfaces in the opening, a second conductor is formed on the barrier layer and fills the opening. Subsequently, the second conductor layer and the barrier layer are removed until the glue layer exposes. A third conductor is defined on the glue layer and the second conductor. The product will solve the problem of high via resistivity caused by stripping solvent and etchant.

Abstract: A method for high-density plasma etching. A substrate is provided. A material layer is formed on the substrate. A patterned photo-resist layer is formed on the oxide layer. The material layer is patterned by the high-density plasma etching, simultaneously, a formation of a barrier layer over the substrate with the patterning process is suppressed and nitrogen gas generated in the patterned photo-resist layer is reduced.

Abstract: A method for controlling the critical dimension of a contact opening in a dielectric layer. A substrate has a dielectric layer formed thereon. A hard mask layer is formed over the dielectric layer. A photosensitive layer is formed over the hard mask layer. The photosensitive layer is patterned to expose a portion of the hard mask layer inside a desired contact opening region. A first etching operation is carried out to remove the hard mask layer within the contact opening region so that a portion of the dielectric layer is exposed. A second etching operation is carried out to remove the dielectric layer within the contact opening region, thereby forming the contact opening.