Patents by Inventor Tony Chiang
Tony Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10833263Abstract: Provided are novel compositions of current compliance layers (CCLs) as well as novel methods of fabricating such CCLs and novel architectures of arranging CCLs and memory cells in memory arrays. A CCL may comprise one of sulfur (S), selenium (Se), and tellurium (Te). The CCL may further comprise one of germanium (Ge) and silicon (Si). CCLs may be fabricated as amorphous structure and remain amorphous when heated to 400° C. or 450° C. and above. In some embodiments, CCLs have crystallization temperatures of greater than 400° C. and, in some embodiments, glass transition temperatures of greater than 400° C. CCLs may be fabricated using atomic layer deposition (ALD) as a nanolaminate of layers having different compositions. The composition, number, and arrangement of the layers in the nanolaminate is specifically selected to yield a desired composition of CCL.Type: GrantFiled: January 7, 2020Date of Patent: November 10, 2020Assignee: INTERMOLECULAR, INC.Inventors: Tony Chiang, Sergey V. Barabash, Karl Littau, Vijay Kris Narasimhan, Stephen Weeks
-
Publication number: 20200288052Abstract: An image capturing device including an image sensing circuit and a processing circuit is provided. The processing circuit controls the image sensing circuit to sense at least one partial frame before sensing a full frame. A number of pixels of the partial frame is less than a number of pixels of the full frame, and exposure time of the partial frame is shorter than exposure time of the full frame. The processing circuit performs an automatic exposure procedure according to the partial frame to calculate a fast exposure time and gain, transforms the fast exposure time and gain into exposure time and gain for the full fame, and control the image sensing circuit to sense the full frame accordingly.Type: ApplicationFiled: March 8, 2019Publication date: September 10, 2020Inventors: Amit MITTRA, Tony CHIANG, Felix SU
-
Publication number: 20200267302Abstract: A camera system is provided and includes a processor, a first camera, a second camera, and a data bus. The processor transmits a first trigger signal to the first camera to enable the first camera outputting first data to the processor through the data bus. The first camera transmits a second trigger signal to the second camera to enable the second camera outputting second data to the processor through the data bus.Type: ApplicationFiled: February 20, 2019Publication date: August 20, 2020Inventors: Amit MITTRA, Tony CHIANG
-
Patent number: 10750077Abstract: A camera system is provided and includes a processor, a first camera, a second camera, and a data bus. The processor transmits a first trigger signal to the first camera to enable the first camera outputting first data to the processor through the data bus. The first camera transmits a second trigger signal to the second camera to enable the second camera outputting second data to the processor through the data bus.Type: GrantFiled: February 20, 2019Date of Patent: August 18, 2020Assignee: Himax Imaging LimitedInventors: Amit Mittra, Tony Chiang
-
Publication number: 20200152867Abstract: Provided are novel compositions of current compliance layers (CCLs) as well as novel methods of fabricating such CCLs and novel architectures of arranging CCLs and memory cells in memory arrays. A CCL may comprise one of sulfur (S), selenium (Se), and tellurium (Te). The CCL may further comprise one of germanium (Ge) and silicon (Si). CCLs may be fabricated as amorphous structure and remain amorphous when heated to 400° C. or 450° C. and above. In some embodiments, CCLs have crystallization temperatures of greater than 400° C. and, in some embodiments, glass transition temperatures of greater than 400° C. CCLs may be fabricated using atomic layer deposition (ALD) as a nanolaminate of layers having different compositions. The composition, number, and arrangement of the layers in the nanolaminate is specifically selected to yield a desired composition of CCL.Type: ApplicationFiled: January 7, 2020Publication date: May 14, 2020Inventors: Tony CHIANG, Sergey V. BARABASH, Karl LITTAU, Vijay Kris NARASIMHAN, Stephen WEEKS
-
Patent number: 10580978Abstract: Provided are novel compositions of current compliance layers (CCLs) as well as novel methods of fabricating such CCLs and novel architectures of arranging CCLs and memory cells in memory arrays. A CCL may comprise one of sulfur (S), selenium (Se), and tellurium (Te). The CCL may further comprise one of germanium (Ge) and silicon (Si). CCLs may be fabricated as amorphous structure and remain amorphous when heated to 400° C. or 450° C. and above. In some embodiments, CCLs have crystallization temperatures of greater than 400° C. and, in some embodiments, glass transition temperatures of greater than 400° C. CCLs may be fabricated using atomic layer deposition (ALD) as a nanolaminate of layers having different compositions. The composition, number, and arrangement of the layers in the nanolaminate is specifically selected to yield a desired composition of CCL.Type: GrantFiled: January 5, 2018Date of Patent: March 3, 2020Assignee: Intermolecular, Inc.Inventors: Tony Chiang, Sergey V Barabash, Karl Littau, Vijay Kris Narasimhan, Stephen Weeks
-
Publication number: 20180198064Abstract: Provided are novel compositions of current compliance layers (CCLs) as well as novel methods of fabricating such CCLs and novel architectures of arranging CCLs and memory cells in memory arrays. A CCL may comprise one of sulfur (S), selenium (Se), and tellurium (Te). The CCL may further comprise one of germanium (Ge) and silicon (Si). CCLs may be fabricated as amorphous structure and remain amorphous when heated to 400° C. or 450° C. and above. In some embodiments, CCLs have crystallization temperatures of greater than 400° C. and, in some embodiments, glass transition temperatures of greater than 400° C. CCLs may be fabricated using atomic layer deposition (ALD) as a nanolaminate of layers having different compositions. The composition, number, and arrangement of the layers in the nanolaminate is specifically selected to yield a desired composition of CCL.Type: ApplicationFiled: January 5, 2018Publication date: July 12, 2018Applicant: Intermolecular, Inc.Inventors: Tony Chiang, Sergey V Barabash, Karl Littau, Vijay Kris Narasimhan, Stephen Weeks
-
Patent number: 9991157Abstract: We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer. A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.Type: GrantFiled: July 8, 2016Date of Patent: June 5, 2018Assignee: APPLIED MATERIALS, INC.Inventors: Tony Chiang, Gongda Yao, Peijun Ding, Fusen E. Chen, Barry L. Chin, Gene Y. Kohara, Zheng Xu, Hong Zhang
-
Publication number: 20160322255Abstract: We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer. A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.Type: ApplicationFiled: July 8, 2016Publication date: November 3, 2016Inventors: Tony CHIANG, Gongda YAO, Peijun DING, Fusen E. CHEN, Barry L. CHIN, Gene Y. KOHARA, Zheng XU, Hong ZHANG
-
Patent number: 9390970Abstract: We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.Type: GrantFiled: April 10, 2007Date of Patent: July 12, 2016Assignee: APPLIED MATERIALS, INC.Inventors: Tony Chiang, Gongda Yao, Peijun Ding, Fusen E. Chen, Barry L. Chin, Gene Y. Kohara, Zheng Xu, Hong Zhang
-
Patent number: 9365217Abstract: An exemplary apparatus and associated method are disclosed for analyzing surface degradation. The apparatus can include a sensor configured to acquire images of a surface; and a processing device configured to correlate the acquired images to a geo-coordinate, to extract at least one property of a surface abnormality identified in at least one of the acquired images, and to generate trend data based on changes over time in the at least one property of the surface abnormality identified in the images, which are correlated to a common geo-coordinate.Type: GrantFiled: June 3, 2013Date of Patent: June 14, 2016Assignee: BOOZ ALLEN HAMILTON INC.Inventors: James Bridgers, Tony Chiang
-
Patent number: 9245848Abstract: Methods of modifying a patterned semiconductor substrate are presented including: providing a patterned semiconductor substrate surface including a dielectric region and a conductive region; and applying an amphiphilic surface modifier to the dielectric region to modify the dielectric region. In some embodiments, modifying the dielectric region includes modifying a wetting angle of the dielectric region. In some embodiments, modifying the wetting angle includes making a surface of the dielectric region hydrophilic. In some embodiments, methods further include applying an aqueous solution to the patterned semiconductor substrate surface. In some embodiments, the conductive region is selectively enhanced by the aqueous solution. In some embodiments, methods further include providing the dielectric region formed of a low-k dielectric material. In some embodiments, applying the amphiphilic surface modifier modifies an interaction of the low-k dielectric region with a subsequent process.Type: GrantFiled: September 17, 2014Date of Patent: January 26, 2016Assignee: Intermolecular, Inc.Inventors: Anh Duong, Tony Chiang, Zachary M. Fresco, Nitin Kumar, Chi-I Lang, Jinhong Tong, Anna Tsizelmon
-
Patent number: 9129894Abstract: Provided are nonvolatile memory assemblies each including a resistive switching layer and current steering element. The steering element may be a transistor connected in series with the switching layer. Resistance control provided by the steering element allows using switching layers requiring low switching voltages and currents. Memory assemblies including such switching layers are easier to embed into integrated circuit chips having other low voltage components, such as logic and digital signal processing components, than, for example, flash memory requiring much higher switching voltages. In some embodiments, provided nonvolatile memory assemblies operate at switching voltages less than about 3.0V and corresponding currents less than 50 microamperes. A memory element may include a metal rich hafnium oxide disposed between a titanium nitride electrode and doped polysilicon electrode. One electrode may be connected to a drain or source of the transistor, while another electrode is connected to a signal line.Type: GrantFiled: September 17, 2012Date of Patent: September 8, 2015Assignee: Intermolecular, Inc.Inventors: Imran Hashim, Tony Chiang, Vidyut Gopal, Yun Wang
-
Patent number: 9076523Abstract: Non linear current response circuits can be used in embedded resistive memory cell for reducing power consumption, together with improving reliability of the memory array. The non linear current response circuits can include two back to back leaky PIN diodes, two parallel anti-directional PIN diodes, two back to back Zener-type metal oxide diodes, or ovonic switching elements, along with current limiting resistor for standby power reduction at the low voltage region. Also, the proposed embedded ReRAM implementation methods based upon 1T2D1R scheme can be integrated into the advanced FEOL process technologies including vertical pillar transistor and/or 3D fin-shaped field effect transistor (FinFET) for realizing a highly compact cell density.Type: GrantFiled: December 13, 2012Date of Patent: July 7, 2015Assignee: Intermolecular, Inc.Inventors: Mankoo Lee, Tony Chiang, Dipankar Pramanik
-
Publication number: 20150147865Abstract: Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode, the switching layer comprising a first metal oxide having a first bandgap greater than 4 electron volts (eV), the switching layer having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a second metal oxide having a second bandgap greater the first bandgap, the coupling layer having a second thickness that is less than 25 percent of the first thickness.Type: ApplicationFiled: February 3, 2015Publication date: May 28, 2015Inventors: Ronald John Kuse, Tony Chiang, Michael Miller, Prashant Phatak, Jinhong Tong
-
Patent number: 9029233Abstract: Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode, the switching layer comprising a first metal oxide having a first bandgap greater than 4 electron volts (eV), the switching layer having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a second metal oxide having a second bandgap greater the first bandgap, the coupling layer having a second thickness that is less than 25 percent of the first thickness.Type: GrantFiled: February 3, 2015Date of Patent: May 12, 2015Assignee: Intermolecular, Inc.Inventors: Ronald John Kuse, Tony Chiang, Michael Miller, Prashant Phatak, Jinhong Tong
-
Patent number: 8975613Abstract: Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode, the switching layer comprising a first metal oxide having a first bandgap greater than 4 electron volts (eV), the switching layer having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a second metal oxide having a second bandgap greater the first bandgap, the coupling layer having a second thickness that is less than 25 percent of the first thickness.Type: GrantFiled: October 30, 2009Date of Patent: March 10, 2015Assignee: Intermolecular, Inc.Inventors: Ronald John Kuse, Tony Chiang, Michael Miller, Prashant Phatak, Jinhong Tong
-
Patent number: 8927322Abstract: The present disclosure is directed to methods of forming different types of Cu2ZnSnS4 (CZTS) solar cells and Copper Indium Gallium DiSelenide (CIGS) solar cells that can be combinatorially varied and evaluated. These methodologies all incorporate the formation of site-isolated regions using a combinatorial processing tool and the use of these site-isolated regions to form the solar cell area. Therefore, multiple solar cells may be rapidly formed on a single substrate for use in combinatorial methodologies. Any of the individual processes of the methods described may be varied combinatorially to test varied process conditions or materials.Type: GrantFiled: May 3, 2011Date of Patent: January 6, 2015Assignee: Intermolecular, Inc.Inventors: Upendra Avachat, Tony Chiang, Craig Hunter, Jian Li, Guizhen Zhang
-
Publication number: 20150001555Abstract: Methods of modifying a patterned semiconductor substrate are presented including: providing a patterned semiconductor substrate surface including a dielectric region and a conductive region; and applying an amphiphilic surface modifier to the dielectric region to modify the dielectric region. In some embodiments, modifying the dielectric region includes modifying a wetting angle of the dielectric region. In some embodiments, modifying the wetting angle includes making a surface of the dielectric region hydrophilic. In some embodiments, methods further include applying an aqueous solution to the patterned semiconductor substrate surface. In some embodiments, the conductive region is selectively enhanced by the aqueous solution. In some embodiments, methods further include providing the dielectric region formed of a low-k dielectric material. In some embodiments, applying the amphiphilic surface modifier modifies an interaction of the low-k dielectric region with a subsequent process.Type: ApplicationFiled: September 17, 2014Publication date: January 1, 2015Inventors: Anh Duong, Tony Chiang, Zachary M. Fresco, Nitin Kumar, Chi-I Lang, Jinhong Tong, Anna Tsizelmon
-
Patent number: 8912524Abstract: Embodiments of the present invention generally relate to a resistive switching nonvolatile memory element that is formed in a resistive switching memory device that may be used in a memory array to store digital data. The memory element is generally constructed as a metal-insulator-metal stack. The resistive switching portion of the memory element includes a getter and/or a defect portion. In general, the getter portion is an area of the memory element that is used to help form, during the resistive switching memory device's fabrication process, a region of the resistive switching layer that has a greater number of vacancies or defects compared to the remainder of resistive switching layer. The defect portion is an area of the memory element that has a greater number of vacancies or defects compared to the remainder of the resistive switching layer, and is formed during the resistive switching memory device's fabrication process.Type: GrantFiled: November 8, 2013Date of Patent: December 16, 2014Assignees: SanDisk 3D LLC, Kabushiki Kaisha ToshibaInventors: Yun Wang, Tony Chiang, Imran Hashim