Abstract: A semiconductor apparatus includes a heatsink plate, a substrate disposed on the heatsink plate, a circuit pattern disposed on the substrate, a semiconductor chip disposed on the circuit pattern, a case fixed to the heatsink plate and surrounding an outer perimeter of the substrate, a terminal attached to the case, and a wire configured to electrically connect the terminal to the circuit pattern or to the semiconductor chip. In a plan view as viewed in the thickness direction of the heatsink plate, a portion of the circuit pattern overlaps the terminal.

Abstract: A semiconductor includes: a substrate; a circuit pattern on the substrate, and including a first region, a second region located away from the first region, and a third region between the first region and the second region; a first chip disposed in the second region and including a diode; a second chip disposed in the third region, the second chip including a vertical transistor having a source pad disposed on a surface opposite to a surface facing the third region in a thickness direction of the substrate, and a gate pad disposed at a position different from the source pad; a first wire including a first bonded portion bonded to the first region, a second bonded portion bonded to the second chip, and a third bonded portion bonded to the first chip; and a second wire arranged to be adjacent to the first wire with the gate pad sandwiched therebetween.

Abstract: A first main surface of a silicon carbide substrate is provided with a first trench and a second trench. The first trench is defined by a first side surface and a first bottom surface. The second trench is defined by a second side surface and a second bottom surface. The silicon carbide substrate includes a first impurity region, a second impurity region, a third impurity region, and a fourth impurity region. A first insulating film is in contact with each of the first side surface and the first bottom surface. A gate electrode is provided on the first insulating film. A second insulating film is in contact with each of the second side surface and the second bottom surface. The second impurity region has a connection region electrically connected to the fourth impurity region and extending toward the fourth impurity region along the second side surface.

Abstract: A transistor includes a wide bandgap semiconductor layer, a gate electrode, a gate pad, and a gate runner. The gate electrode extends to a region where the gate pad is located and a region where the gate runner is located. The gate pad is connected to the gate electrode. The gate runner is connected to the gate electrode. The gate electrode includes a first region connected to the gate pad, a second region connected to the gate runner, and a third region and a fourth region arranged between the first and second regions in different positions in a first direction. In a cross section perpendicular to the first direction, the gate electrode in the fourth region has a cross-sectional area smaller than that of the gate electrode in the third region.

Abstract: A silicon carbide semiconductor device to be a vertical transistor includes: a silicon carbide semiconductor first layer 21 of a first conductivity type; a silicon carbide semiconductor second layer 22 of a second conductivity type that is different from the first conductivity type on the first layer 21; a silicon carbide semiconductor third layer 120 of the first conductivity type on the second layer 22; and a groove 30 having a sidewall 30a at portions of the third layer 120, the second layer 22, and the first layer 21, wherein the third layer 120 has a first area 121 facing the sidewall 30a of the groove 30 and a second area 122 further away from the sidewall 30a of the groove 30 than the first area 121, wherein the second area 122 and the first area 121 are continuous, and wherein the second area 122 is provided deeper than the first area 121 from a surface side of the third layer 130 toward the first layer 21.

Abstract: A semiconductor includes: a substrate; a circuit pattern on the substrate, and including a first region, a second region located away from the first region, and a third region between the first region and the second region; a first chip disposed in the second region and including a diode; a second chip disposed in the third region, the second chip including a vertical transistor having a source pad disposed on a surface opposite to a surface facing the third region in a thickness direction of the substrate, and a gate pad disposed at a position different from the source pad; a first wire including a first bonded portion bonded to the first region, a second bonded portion bonded to the second chip, and a third bonded portion bonded to the first chip; and a second wire arranged to be adjacent to the first wire with the gate pad sandwiched therebetween.

Abstract: A silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The first main surface is provided with a gate trench having a side surface and a bottom surface contiguous to the side surface. The gate insulating film is in contact with each of the side surface and the bottom surface. The gate electrode is provided on the gate insulating film. The separation insulating film is provided on the gate electrode. The first electrode is provided on the separation insulating film. The second electrode is provided on the second main surface. The separation insulating film electrically separates the gate electrode and the first electrode from each other. Each of the gate insulating film, the gate electrode, and the separation insulating film, and a portion of the first electrode are provided in the gate trench.

Abstract: A silicon carbide semiconductor device has a gate insulating film, a first gate electrode, a first electrode, a second electrode, and a gate runner. A silicon carbide substrate has a first main surface and a second main surface. The silicon carbide substrate includes a first impurity region, a second impurity region, and a third impurity region. The first main surface is provided with a gate electrode trench and a gate runner trench. The gate electrode trench is defined by a side surface and a bottom surface continuous to the side surface. The gate insulating film is in contact with both the side surface and the bottom surface. The first gate electrode is provided on the gate insulating film. The second gate electrode is provided in the gate runner trench, and is electrically connected to the first gate electrode. The gate runner is provided on the second gate electrode.

Abstract: A silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. A gate pad faces the first main surface. A drain electrode is in contact with the second main surface. The silicon carbide substrate includes a first impurity region constituting the second main surface and having a first conductivity type, a second impurity region provided on the first impurity region and having a second conductivity type different from the first conductivity type, a third impurity region provided on the second impurity region and having the first conductivity type, and a fourth impurity region provided on the third impurity region, constituting the first main surface, and having the second conductivity type. Each of the first impurity region, the second impurity region, the third impurity region, and the fourth impurity region is located between the gate pad and the drain electrode.

Abstract: The sense region is spaced from the active region. The isolation trench surrounds the sense region and isolates the sense region from the active region. The active region is provided with a first gate trench defined by a first side surface and a first bottom surface continuing to the first side surface. The first insulating film is in contact with both the first side surface and the first bottom surface. The first conductor is provided on the first insulating film. The second insulating film is provided in the isolation trench. The second conductor is provided on the second insulating film. The isolation trench reaches a first impurity region. The first insulating film is made of a material identical to that of the second insulating film. The first conductor is made of a material identical to that of the second conductor and is electrically isolated from the second conductor.

Abstract: A first main surface of a silicon carbide substrate is provided with a first trench and a second trench. The first trench is defined by a first side surface and a first bottom surface. The second trench is defined by a second side surface and a second bottom surface. The silicon carbide substrate includes a first impurity region, a second impurity region, a third impurity region, and a fourth impurity region. A first insulating film is in contact with each of the first side surface and the first bottom surface. A gate electrode is provided on the first insulating film. A second insulating film is in contact with each of the second side surface and the second bottom surface. The second impurity region has a connection region electrically connected to the fourth impurity region and extending toward the fourth impurity region along the second side surface.

Abstract: A semiconductor apparatus includes a heatsink plate, a substrate disposed on the heatsink plate, a circuit pattern disposed on the substrate, a semiconductor chip disposed on the circuit pattern, a case fixed to the heatsink plate and surrounding an outer perimeter of the substrate, a terminal attached to the case, and a wire configured to electrically connect the terminal to the circuit pattern or to the semiconductor chip. In a plan view as viewed in the thickness direction of the heatsink plate, a portion of the circuit pattern overlaps the terminal.

Abstract: A silicon carbide semiconductor device to be a vertical transistor includes: a silicon carbide semiconductor first layer 21 of a first conductivity type; a silicon carbide semiconductor second layer 22 of a second conductivity type that is different from the first conductivity type on the first layer 21; a silicon carbide semiconductor third layer 120 of the first conductivity type on the second layer 22; and a groove 30 having a sidewall 30a at portions of the third layer 120, the second layer 22, and the first layer 21, wherein the third layer 120 has a first area 121 facing the sidewall 30a of the groove 30 and a second area 122 further away from the sidewall 30a of the groove 30 than the first area 121, wherein the second area 122 and the first area 121 are continuous, and wherein the second area 122 is provided deeper than the first area 121 from a surface side of the third layer 130 toward the first layer 21.

Abstract: A silicon carbide substrate has at least one of a first structure and a second structure. The first structure is such that a first impurity region is in contact with a second impurity region, a third impurity region is separated from a fourth impurity region by a second drift region, and the second impurity region has a width greater than a width of the fourth impurity region in a direction parallel to a first main surface. The second structure is such that the first impurity region is separated from the second impurity region by a first drift region, the third impurity region is in contact with the fourth impurity region, and the fourth impurity region has a width greater than a width of the second impurity region in the direction parallel to the first main surface.

Abstract: A silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. A gate pad faces the first main surface. A drain electrode is in contact with the second main surface. The silicon carbide substrate includes a first impurity region constituting the second main surface and having a first conductivity type, a second impurity region provided on the first impurity region and having a second conductivity type different from the first conductivity type, a third impurity region provided on the second impurity region and having the first conductivity type, and a fourth impurity region provided on the third impurity region, constituting the first main surface, and having the second conductivity type. Each of the first impurity region, the second impurity region, the third impurity region, and the fourth impurity region is located between the gate pad and the drain electrode.

Abstract: A silicon carbide semiconductor device has a gate insulating film, a first gate electrode, a first electrode, a second electrode, and a gate runner. A silicon carbide substrate has a first main surface and a second main surface. The silicon carbide substrate includes a first impurity region, a second impurity region, and a third impurity region. The first main surface is provided with a gate electrode trench and a gate runner trench. The gate electrode trench is defined by a side surface and a bottom surface continuous to the side surface. The gate insulating film is in contact with both the side surface and the bottom surface. The first gate electrode is provided on the gate insulating film. The second gate electrode is provided in the gate runner trench, and is electrically connected to the first gate electrode. The gate runner is provided on the second gate electrode.

Abstract: The sense region is spaced from the active region. The isolation trench surrounds the sense region and isolates the sense region from the active region. The active region is provided with a first gate trench defined by a first side surface and a first bottom surface continuing to the first side surface. The first insulating film is in contact with both the first side surface and the first bottom surface. The first conductor is provided on the first insulating film. The second insulating film is provided in the isolation trench. The second conductor is provided on the second insulating film. The isolation trench reaches a first impurity region. The first insulating film is made of a material identical to that of the second insulating film. The first conductor is made of a material identical to that of the second conductor and is electrically isolated from the second conductor.

Abstract: The side surface has a first outer end surface. The bottom surface has a first bottom portion continuous to the first outer end surface, and a second bottom portion continuous to the first bottom portion and located on a side opposite to the inner end surface with respect to the first bottom portion. A silicon carbide substrate has a first region and a second region located between the at least one gate trench and a second main surface, and spaced from each other with a drift region being sandwiched therebetween. In a direction parallel to the first outer end surface, a spacing between the first region and the second region located between the first bottom portion and the second main surface is smaller than a spacing between the first region and the second region located between the second bottom portion and the second main surface.

Abstract: A silicon carbide semiconductor device includes: a silicon carbide substrate; a first silicon carbide layer disposed on the silicon carbide substrate; a second silicon carbide layer disposed on the first silicon carbide layer; a third silicon carbide layer disposed on the second silicon carbide layer; a fourth silicon carbide layer disposed on the third silicon carbide layer; and a first impurity region formed to extend through the second silicon carbide layer, the third silicon carbide layer and the fourth silicon carbide layer. A trench is formed in the silicon carbide semiconductor device. The silicon carbide semiconductor device includes: a gate insulating film in contact with a wall of the trench; a gate electrode; a second impurity region disposed below the trench; a third impurity region formed below the first impurity region; and a fourth impurity region formed between the second impurity region and the third impurity region.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate and a gate insulating film. The silicon carbide substrate includes a first impurity region, a second impurity region, a third impurity region, a fourth impurity region, a fifth impurity region, and a sixth impurity region. A first main surface of the silicon carbide substrate is provided with a trench defined by a side surface and a bottom portion. The sixth impurity region includes a first region which faces the bottom portion and a second region which faces a second main surface of the silicon carbide substrate. The first region is higher in impurity concentration than the second region. In a direction perpendicular to the second main surface, a fifth main surface of the fourth impurity region is located between a sixth main surface of the second impurity region and the second main surface.