Abstract: A silicon carbide substrate has at least one of a first structure and a second structure. The first structure is such that a first impurity region is in contact with a second impurity region, a third impurity region is separated from a fourth impurity region by a second drift region, and the second impurity region has a width greater than a width of the fourth impurity region in a direction parallel to a first main surface. The second structure is such that the first impurity region is separated from the second impurity region by a first drift region, the third impurity region is in contact with the fourth impurity region, and the fourth impurity region has a width greater than a width of the second impurity region in the direction parallel to the first main surface.

Abstract: A silicon carbide substrate includes a first impurity region, a second impurity region in contact with the first impurity region and having p type, a third impurity region on the first impurity region and the second impurity region and having n type, a body region, and a source region. A gate insulating film is in contact with the source region, the body region and the third impurity region at a side surface, and in contact with the third impurity region at a bottom surface. When viewed in a direction perpendicular to a main surface, the second impurity region contains the bottom surface, and an area of the second impurity region is greater than an area of the bottom surface, and is not more than three times the area of the bottom surface. An impurity concentration of the second impurity region exceeds 1×1019 cm?3, and is not more than 1×1021 cm?3.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate and a gate insulating film. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The gate insulating film is provided on the first main surface. The silicon carbide substrate includes a first body region having p type, a second body region having p type, and a JFET region provided between the first body region and the second body region and having n type. The JFET region has both a first impurity capable of providing the p type and a second impurity capable of providing the n type. A concentration of the second impurity is higher than a concentration of the first impurity. The silicon carbide semiconductor device capable of suppressing dielectric breakdown of the gate insulating film is provided.

Abstract: A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor layer including a wide bandgap semiconductor, the semiconductor layer having an element region and an outer peripheral region surrounding an outer periphery of the element region when viewed two-dimensionally, forming a step portion surrounding the outer periphery of the element region in the outer peripheral region, and forming a metal layer along the step portion. The step portion has a sidewall recessed downward from a main surface of the element region in a cross section parallel to a thickness direction of the semiconductor layer, and the metal layer extends to cover at least a portion of the sidewall. The method of manufacturing a semiconductor device further includes the step of dividing the semiconductor layer into the element regions on an outside of the step portion when viewed from the element region.

Abstract: The side surface has a first outer end surface. The bottom surface has a first bottom portion continuous to the first outer end surface, and a second bottom portion continuous to the first bottom portion and located on a side opposite to the inner end surface with respect to the first bottom portion. A silicon carbide substrate has a first region and a second region located between the at least one gate trench and a second main surface, and spaced from each other with a drift region being sandwiched therebetween. In a direction parallel to the first outer end surface, a spacing between the first region and the second region located between the first bottom portion and the second main surface is smaller than a spacing between the first region and the second region located between the second bottom portion and the second main surface.

Abstract: A silicon carbide semiconductor device includes: a drift layer in contact with a first main surface and having a first conductivity type; a body region located in the drift layer, in contact with the first main surface, and having a second conductivity type; and a protruding portion having the second conductivity type and connected to a bottom of the body region. A manufacturing method includes forming, in the drift layer of a silicon carbide substrate, by ion implantation, the body region, the protruding portion, a JTE region, and at least one guard ring region, each having the second conductivity type.

Abstract: A silicon carbide semiconductor device includes: a silicon carbide substrate; a first silicon carbide layer disposed on the silicon carbide substrate; a second silicon carbide layer disposed on the first silicon carbide layer; a third silicon carbide layer disposed on the second silicon carbide layer; a fourth silicon carbide layer disposed on the third silicon carbide layer; and a first impurity region formed to extend through the second silicon carbide layer, the third silicon carbide layer and the fourth silicon carbide layer. A trench is formed in the silicon carbide semiconductor device. The silicon carbide semiconductor device includes: a gate insulating film in contact with a wall of the trench; a gate electrode; a second impurity region disposed below the trench; a third impurity region formed below the first impurity region; and a fourth impurity region formed between the second impurity region and the third impurity region.

Abstract: A first main surface is provided with: a gate trench defined by a first side surface and a first bottom surface; and a source trench defined by a second side surface and a second bottom surface. A silicon carbide substrate includes a drift region, a body region, a source region, a first region, and a second region. The first region is in contact with the second region. A gate insulating film is in contact with the drift region, the body region, and the source region at the first side surface, and is in contact with the drift region at the first bottom surface. A source electrode is in contact with the second region at the second side surface and the second bottom surface.

Abstract: A silicon carbide substrate includes a first impurity region, a second impurity region in contact with the first impurity region and having p type, a third impurity region on the first impurity region and the second impurity region and having n type, a body region, and a source region. A gate insulating film is in contact with the source region, the body region and the third impurity region at a side surface, and in contact with the third impurity region at a bottom surface. When viewed in a direction perpendicular to a main surface, the second impurity region contains the bottom surface, and an area of the second impurity region is greater than an area of the bottom surface, and is not more than three times the area of the bottom surface. An impurity concentration of the second impurity region exceeds 1×1019 cm?3, and is not more than 1×1021 cm?3.

Abstract: A silicon carbide layer includes a drift region, a body region and a source region. The drift region constitutes a first main surface and has a first conductivity type. The body region is provided on the drift region, and has a second conductivity type. It is provided on the body region to be separated from the drift region, constitutes a second main surface, and has the first conductivity type. The silicon carbide layer is provided with a trench including a first side wall portion and a first bottom portion. The silicon carbide layer is embedded in the drift region to face the first bottom portion, and includes a second conductivity type region having the second conductivity type. The second conductivity type region is electrically connected to the source region.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate and a gate insulating film. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The gate insulating film is provided on the first main surface. The silicon carbide substrate includes a first body region having p type, a second body region having p type, and a JFET region provided between the first body region and the second body region and having n type. The JFET region has both a first impurity capable of providing the p type and a second impurity capable of providing the n type. A concentration of the second impurity is higher than a concentration of the first impurity. The silicon carbide semiconductor device capable of suppressing dielectric breakdown of the gate insulating film is provided.

Abstract: A method for manufacturing a silicon carbide epitaxial substrate includes epitaxially growing a first layer on a silicon carbide single crystal substrate, and forming a second layer at an outermost surface of the first layer. The second layer has a chemical composition or density different from that of the first layer. A ratio of a thickness of the second layer to a thickness of the first layer is more than 0% and less than or equal to 10%.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate and a gate insulating film. The silicon carbide substrate includes a first impurity region, a second impurity region, a third impurity region, a fourth impurity region, a fifth impurity region, and a sixth impurity region. A first main surface of the silicon carbide substrate is provided with a trench defined by a side surface and a bottom portion. The sixth impurity region includes a first region which faces the bottom portion and a second region which faces a second main surface of the silicon carbide substrate. The first region is higher in impurity concentration than the second region. In a direction perpendicular to the second main surface, a fifth main surface of the fourth impurity region is located between a sixth main surface of the second impurity region and the second main surface.

Abstract: A method for manufacturing a silicon carbide semiconductor device includes the steps of preparing a silicon carbide substrate having a first main surface and a second main surface located on a side opposite to the first main surface, forming an epitaxial layer on the first main surface, the epitaxial layer having a first conductivity type and having a third main surface located on a side opposite to a side on which the silicon carbide substrate is located, forming a trench, which includes side walls intersecting with the third main surface and a bottom portion connected to the side walls, in the epitaxial layer, widening an opening of the trench, and forming an embedded region, which has a second conductivity type different from the first conductivity type, in the trench. The epitaxial layer adjacent to the embedded region and the embedded region constitute a superjunction structure.

Abstract: A silicon carbide layer includes a drift region, a body region and a source region. The drift region constitutes a first main surface and has a first conductivity type. The body region is provided on the drift region, and has a second conductivity type. It is provided on the body region to be separated from the drift region, constitutes a second main surface, and has the first conductivity type. The silicon carbide layer is provided with a trench including a first side wall portion and a first bottom portion. The silicon carbide layer is embedded in the drift region to face the first bottom portion, and includes a second conductivity type region having the second conductivity type. The second conductivity type region is electrically connected to the source region.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate and a gate insulating film. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The gate insulating film is provided on the first main surface. The silicon carbide substrate includes a first body region having p type, a second body region having p type, and a JFET region provided between the first body region and the second body region and having n type. The JFET region has both a first impurity capable of providing the p type and a second impurity capable of providing the n type. A concentration of the second impurity is higher than a concentration of the first impurity. The silicon carbide semiconductor device capable of suppressing dielectric breakdown of the gate insulating film is provided.

Abstract: A silicon carbide semiconductor device includes a gate insulating film and a gate electrode. A first main surface is provided with a trench defined by a side surface penetrating a third impurity region and a second impurity region to reach a first impurity region, and a bottom provided continuously with the side surface. In a stress test in which a gate voltage of at least one of ?10 V and 20 V is applied to the gate electrode for 100 hours at a temperature of 175° C., where a threshold voltage before the stress test is defined as a first threshold voltage and a threshold voltage after the stress test is defined as a second threshold voltage, an absolute value of a difference between the first threshold voltage and the second threshold voltage is not more than 0.25 V. The second threshold voltage is not less than 2.5 V.

Abstract: A silicon carbide semiconductor device includes: a drift layer in contact with a first main surface and having a first conductivity type; a body region located in the drift layer, in contact with the first main surface, and having a second conductivity type; and a protruding portion having the second conductivity type and connected to a bottom of the body region. A manufacturing method includes forming, in the drift layer of a silicon carbide substrate, by ion implantation, the body region, the protruding portion, a JTE region, and at least one guard ring region, each having the second conductivity type.

Abstract: A silicon carbide semiconductor device includes a gate insulating film and a gate electrode. A first main surface is provided with a trench defined by a side surface penetrating a third impurity region and a second impurity region to reach a first impurity region, and a bottom provided continuously with the side surface. In a stress test in which a gate voltage of at least one of ?10 V and 20 V is applied to the gate electrode for 100 hours at a temperature of 175° C., where a threshold voltage before the stress test is defined as a first threshold voltage and a threshold voltage after the stress test is defined as a second threshold voltage, an absolute value of a difference between the first threshold voltage and the second threshold voltage is not more than 0.25 V. The second threshold voltage is not less than 2.5 V.

Abstract: A method for manufacturing a silicon carbide semiconductor device includes the steps of preparing a silicon carbide substrate having a first main surface and a second main surface located on a side opposite to the first main surface, forming an epitaxial layer on the first main surface, the epitaxial layer having a first conductivity type and having a third main surface located on a side opposite to a side on which the silicon carbide substrate is located, forming a trench, which includes side walls intersecting with the third main surface and a bottom portion connected to the side walls, in the epitaxial layer, widening an opening of the trench, and forming an embedded region, which has a second conductivity type different from the first conductivity type, in the trench. The epitaxial layer adjacent to the embedded region and the embedded region constitute a superjunction structure.