Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate and a gate insulating film. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The gate insulating film is provided on the first main surface. The silicon carbide substrate includes a first body region having p type, a second body region having p type, and a JFET region provided between the first body region and the second body region and having n type. The JFET region has both a first impurity capable of providing the p type and a second impurity capable of providing the n type. A concentration of the second impurity is higher than a concentration of the first impurity. The silicon carbide semiconductor device capable of suppressing dielectric breakdown of the gate insulating film is provided.

Abstract: An SiC semiconductor device includes an SiC layer including a drift region forming a surface and a body region forming a part of a surface and being in contact with the drift region, a drain electrode electrically connected to a region on a side of the surface in the drift region, and a source electrode electrically connected to the body region. Main carriers which pass through the drift region and migrate between the drain electrode and the source electrode are only electrons. Z1/2 center is introduced into the drift region at a concentration not lower than 1×1013 cm?3 and not higher than 1×1015 cm?3.

Abstract: A method for manufacturing a silicon carbide semiconductor device includes the steps of preparing a silicon carbide substrate having a first main surface and a second main surface located on a side opposite to the first main surface, forming an epitaxial layer on the first main surface, the epitaxial layer having a first conductivity type and having a third main surface located on a side opposite to a side on which the silicon carbide substrate is located, forming a trench, which includes side walls intersecting with the third main surface and a bottom portion connected to the side walls, in the epitaxial layer, widening an opening of the trench, and forming an embedded region, which has a second conductivity type different from the first conductivity type, in the trench. The epitaxial layer adjacent to the embedded region and the embedded region constitute a superjunction structure.

Abstract: A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor layer including a wide bandgap semiconductor, the semiconductor layer having an element region and an outer peripheral region surrounding an outer periphery of the element region when viewed two-dimensionally, forming a step portion surrounding the outer periphery of the element region in the outer peripheral region, and forming a metal layer along the step portion. The step portion has a sidewall recessed downward from a main surface of the element region in a cross section parallel to a thickness direction of the semiconductor layer, and the metal layer extends to cover at least a portion of the sidewall. The method of manufacturing a semiconductor device further includes the step of dividing the semiconductor layer into the element regions on an outside of the step portion when viewed from the element region.

Abstract: A silicon carbide semiconductor device has a silicon carbide substrate and an insulating film. The silicon carbide substrate includes a termination region having a peripheral edge, and an element region surrounded by the termination region. The insulating film is provided on the termination region. The termination region includes a first impurity region having a first conductivity type, and a field stop region having the first conductivity type, being in contact with the first impurity region and having a higher impurity concentration than the first impurity region. The field stop region is at least partially exposed at the peripheral edge.

Abstract: A silicon carbide single-crystal substrate having a first main surface angled off relative to a {0001} plane, and a first peripheral edge provided continuously with the first main surface is prepared. A silicon carbide epitaxial layer is formed on the first main surface. The silicon carbide epitaxial layer has a second main surface in contact with the first main surface, a third main surface opposite to the second main surface, and a second peripheral edge provided continuously with each of the second main surface and the third main surface. A peripheral region including the first peripheral edge and the second peripheral edge is removed. The silicon carbide epitaxial layer has a thickness of not less than 50 ?m in a direction perpendicular to the third main surface.

Abstract: A silicon carbide semiconductor device includes a silicon carbide layer having a first main surface and a second main surface opposite to the first main surface. In the second main surface of the silicon carbide layer, a trench having a depth in a direction from the second main surface toward the first main surface is provided, and the trench has a sidewall portion where a second layer and a third layer are exposed and a bottom portion, where a first layer is exposed. A position of the bottom portion of the trench in a direction of depth of the trench is located on a side of the second main surface relative to a site located closest to the first main surface in a region where the second layer and the first layer are in contact with each other, or located as deep as the site in the direction of depth.

Abstract: A method of manufacturing a semiconductor device includes preparing a semiconductor layer having an element region and an outer peripheral region, forming a step portion surrounding the outer periphery of the element region in the outer peripheral region, and forming a metal layer along the step portion. The metal layer extends to cover at least a portion of a sidewall of the step portion. The method of manufacturing the semiconductor device further includes dividing the semiconductor layer into element regions on an outside of the step portion when viewed from the element region.

Abstract: A silicon carbide semiconductor device includes a silicon carbide layer having a first main surface and a second main surface opposite to the first main surface. In the second main surface of the silicon carbide layer, a trench having a depth in a direction from the second main surface toward the first main surface is provided, and the trench has a sidewall portion where a second layer and a third layer are exposed and a bottom portion, where a first layer is exposed. A position of the bottom portion of the trench in a direction of depth of the trench is located on a side of the second main surface relative to a site located closest to the first main surface in a region where the second layer and the first layer are in contact with each other, or located as deep as the site in the direction of depth.

Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor layer, a gate insulating film formed on the silicon carbide semiconductor layer, and a gate electrode provided on the gate insulating film, wherein the gate electrode has a polysilicon layer at least on a side of an interface with the gate insulating film, and the gate insulating film has an oxide film derived from the polysilicon layer, at an interface between the gate insulating film and the polysilicon layer of the gate electrode.

Abstract: A silicon carbide semiconductor device includes: a silicon carbide semiconductor layer having a main surface, the main surface being provided with a trench which has a bottom portion and a sidewall inclined with respect to the main surface; a gate insulating film covering each of the bottom portion and the sidewall; a gate electrode provided at least on the gate insulating film; and an upper insulating film provided on the main surface and having a part which protrudes into the trench.

Abstract: A silicon carbide epitaxial layer includes: a first impurity region; a second impurity region; and a third impurity region. A gate insulating film is in contact with the first impurity region, the second impurity region, and the third impurity region. A groove portion is formed in a surface of the first impurity region, the surface being in contact with the gate insulating film, the groove portion extending in one direction along the surface, a width of the groove portion in the one direction being twice or more as large as a width of the groove portion in a direction perpendicular to the one direction, a maximum depth of the groove portion from the surface being not more than 10 nm.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate and a gate electrode. The silicon carbide substrate includes a first source region and a second source region, a first body region, a second body region, a first drift region, a second drift region, a third drift region, and a first connection region. The first connection region is provided to include a first intersection and a second intersection, the first intersection being an intersection of a straight line along a first straight-line portion and a straight line along a second straight-line portion, the second intersection being an intersection of a straight line along a third straight-line portion and a straight line along a fourth straight-line portion, and the first connection region has a second conductivity type.

Abstract: A silicon carbide substrate includes a first impurity region, a well region in contact with the first impurity region, and a second impurity region separated from the first impurity region by the well region. A first main surface includes a first region in contact with a channel region, and a second region different from the first region. A silicon-containing material is formed on the second region. A first silicon dioxide region is formed on the first region. A second silicon dioxide region is formed by oxidizing the silicon-containing material. A gate runner is electrically connected to a gate electrode and formed in a position facing the second silicon dioxide region. Consequently, a silicon carbide semiconductor device capable of achieving improved insulation performance between the gate runner and the substrate while the surface roughness of the substrate is suppressed, and a method of manufacturing the same can be provided.

Abstract: There is provided a silicon carbide semiconductor device allowing for integration of a transistor element and a Schottky barrier diode while avoiding reduction of an active region and decrease of a breakdown voltage. A silicon carbide semiconductor device includes a silicon carbide layer. The silicon carbide layer includes: a first region defining an outer circumference portion of an element region in which a transistor element is provided; and a JTE region provided external to the first region in a drift layer and electrically connected to the first region. The first region is provided with at least one opening through which the drift layer is exposed. The silicon carbide semiconductor device further includes a Schottky electrode provided in the opening and forming a Schottky junction with the drift layer.

Abstract: A method of producing a silicon carbide epitaxial substrate includes steps of: preparing a silicon carbide substrate; and forming a silicon carbide layer on the silicon carbide substrate. In this production method, in the step of forming the silicon carbide layer, a step of growing an epitaxial layer and a step of polishing a surface of the epitaxial layer are repeated twice or more.

Abstract: A gate insulating film is provided on a trench. The gate insulating film has a trench insulating film and a bottom insulating film. The trench insulating film covers each of a side wall and a bottom portion. The bottom insulating film is provided on the bottom portion with a trench insulating film being interposed therebetween. The bottom insulating film has a carbon atom concentration lower than that of the trench insulating film. The gate electrode is in contact with a portion of the trench insulating film on the side wall. Accordingly, a low threshold voltage and a large breakdown voltage can be attained.

Abstract: A silicon carbide semiconductor device includes a silicon carbide layer having a first main surface and a second main surface opposite to the first main surface. In the second main surface of the silicon carbide layer, a trench having a depth in a direction from the second main surface toward the first main surface is provided, and the trench has a sidewall portion where a second layer and a third layer are exposed and a bottom portion, where a first layer is exposed. A position of the bottom portion of the trench in a direction of depth of the trench is located on a side of the second main surface relative to a site located closest to the first main surface in a region where the second layer and the first layer are in contact with each other, or located as deep as the site in the direction of depth.

Abstract: A silicon carbide semiconductor device includes an impurity region including a p type impurity and disposed within a silicon carbide layer to surround an element region as seen in plan view. The impurity region has a peak concentration of the p type impurity at a position within the silicon carbide layer distant from a first main surface. The peak concentration is not less than 1×1016 cm?3 and not more than 5×1017 cm?3. The impurity region is formed by implanting ions of the p type impurity into the silicon carbide layer. Then, a silicon dioxide film is formed to cover the first main surface of the silicon carbide layer by performing a thermal oxidation process on the silicon carbide layer, and the concentration of the p type impurity in the vicinity of the first main surface is lowered.

Abstract: A silicon carbide semiconductor device has a silicon carbide substrate, a gate insulating film, and a gate electrode. Silicon carbide substrate includes a first impurity region having a first conductivity type, a well region being in contact with the first impurity region and having a second conductivity type which is different from the first conductivity type, and a second impurity region separated from the first impurity region by the well region and having the first conductivity type. The gate insulating film is in contact with the first impurity region and the well region. The gate electrode is in contact with the gate insulating film and is arranged opposite to the well region with respect to the gate insulating film. A specific on-resistance at a voltage which is half a gate driving voltage applied to the gate electrode is smaller than twice the specific on-resistance at the gate driving voltage.