Abstract: An MOSFET includes a silicon carbide substrate, an active layer, a gate oxide film, and a gate electrode. The active layer includes a body region where an inversion layer is formed at a region in contact with the gate oxide film by application of voltage to the gate electrode. The body region includes a low concentration region arranged at a region where an inversion layer is formed, and containing impurities of low concentration, and a high concentration region adjacent to the low concentration region in the carrier mobile direction in the inversion layer, arranged in a region where the inversion layer is formed, and containing impurities higher in concentration than in the low concentration region.

Abstract: A substrate is provided with a main surface having an off angle of 5° or smaller relative to a reference plane. The reference plane is a {000-1} plane in the case of hexagonal system and is a {111} plane in the case of cubic system. A silicon carbide layer is epitaxially formed on the main surface of the substrate. The silicon carbide layer is provided with a trench having first and second side walls opposite to each other. Each of the first and second side walls includes a channel region. Further, each of the first and second side walls substantially includes one of a {0-33-8} plane and a {01-1-4} plane in the case of the hexagonal system and substantially includes a {100} plane in the case of the cubic system.

Abstract: A silicon carbide semiconductor device having excellent electrical characteristics including channel mobility and a method for manufacturing the same are provided. The method for manufacturing a silicon carbide semiconductor device includes: an epitaxial layer forming step of preparing a semiconductor film of silicon carbide; a gate insulating film forming step of forming an oxide film on a surface of the semiconductor film; a nitrogen annealing step of performing heat treatment on the semiconductor film on which the oxide film is formed, in a nitrogen-containing atmosphere; and a post heat treatment step of performing, after the nitrogen annealing step, post heat treatment on the semiconductor film on which the oxide film is formed, in an atmosphere containing an inert gas. The heat treatment temperature in the post heat treatment step is higher than that in the nitrogen annealing step and lower than a melting point of the oxide film.

Abstract: An MOSFET includes a silicon carbide substrate, an active layer, a gate oxide film, and a gate electrode. The active layer includes a body region where an inversion layer is formed at a region in contact with the gate oxide film by application of voltage to the gate electrode. The body region includes a low concentration region arranged at a region where an inversion layer is formed, and containing impurities of low concentration, and a high concentration region adjacent to the low concentration region in the carrier mobile direction in the inversion layer, arranged in a region where the inversion layer is formed, and containing impurities higher in concentration than in the low concentration region.

Abstract: A first layer has n type conductivity. A second layer is epitaxially formed on the first layer and having p type conductivity. A third layer is on the second layer and having n type conductivity. ND is defined to represent a concentration of a donor type impurity. NA is defined to represent a concentration of an acceptor type impurity. D1 is defined to represent a location in the first layer away from an interface between the first layer and the second layer in a depth direction. D1 in which 1?ND/NA?50 is satisfied is within 1 ?m therefrom. A gate trench is provided to extend through the third layer and the second layer to reach the first layer. A gate insulating film covers a side wall of the gate trench. A gate electrode is embedded in the gate trench with the gate insulating film interposed therebetween.

Abstract: A silicon carbide substrate having a main face is prepared. By applying thermal oxidation to the main face of the silicon carbide substrate at a first temperature, an oxide film is formed on the main face. After the oxide film is formed, heat treatment is applied to the silicon carbide substrate at a second temperature higher than the first temperature. An opening exposing a portion of the main face is formed at the oxide film. A Schottky electrode is formed on the main face exposed by the opening.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate. The silicon carbide substrate is composed of an element region provided with a semiconductor element portion and a termination region surrounding the element region as viewed in a plan view. The semiconductor element portion includes a drift region having a first conductivity type. The termination region includes a first electric field relaxing region contacting the element region and having a second conductivity type different from the first conductivity type, and a second electric field relaxing region arranged outside the first electric field relaxing region as viewed in the plan view, having the second conductivity type, and spaced from the first electric field relaxing region. A ratio calculated by dividing a width of the first electric field relaxing region by a thickness of the drift region is not less than 0.5 and not more than 1.83.

Abstract: A wide gap semiconductor device includes a substrate and a Schottky electrode. The substrate formed of a wide gap semiconductor material has a main face, and includes a first-conductivity-type region and a second-conductivity-type region. The Schottky electrode is arranged adjoining the main face of the substrate. At the substrate, there is foamed a trench having a side face continuous with the main face and a bottom continuous with the side face. The Schottky electrode adjoins the first-conductivity-type region at the side face of the trench and the main face, and adjoins the second-conductivity-type region at the bottom of the trench. The side face of the trench is inclined relative to the main face of the substrate.

Abstract: The substrate is made of a compound semiconductor, and has a recess, which opens at one main surface and has side wall surfaces when viewed in a cross section along a thickness direction. The gate insulating film is disposed on and in contact with each of the side wall surfaces. The substrate includes a source region having first conductivity type and disposed to be exposed at the side wall surface; and a body region having second conductivity type and disposed in contact with the source region at a side opposite to the one main surface so as to be exposed at the side wall surface, when viewed from the source region. The recess has a closed shape when viewed in a plan view. The side wall surfaces provide an outwardly projecting shape in every direction when viewed from an arbitrary location in the recess.

Abstract: A first drift layer has a first surface facing a first electrode and electrically connected to a first electrode, and a second surface opposite to the first surface. The first drift layer has an impurity concentration NA. A relaxation region is provided in a portion of the second surface of the first drift layer. The first drift layer and the second drift layer form a drift region in which the relaxation region is buried. The second drift layer has an impurity concentration NB, NB>NA being satisfied. A body region, a source region, and a second electrode are provided on the second drift layer.

Abstract: A silicon carbide substrate includes: an n type drift layer having a first surface and a second surface opposite to each other; a p type body region provided in the first surface of the n type drift layer; and an n type emitter region provided on the p type body region and separated from the n type drift layer by the p type body region. A gate insulating film is provided on the p type body region so as to connect the n type drift layer and the n type emitter region to each other. A p type Si collector layer is directly provided on the silicon carbide substrate to face the second surface of the n type drift layer.

Abstract: The substrate is made of a compound semiconductor and has a plurality of first recesses, each of which opens at one main surface thereof and has a first side wall surface. The gate insulating film is disposed on and in contact with the first side wall surface. The gate electrode is disposed on and in contact with the gate insulating film. The substrate include: a source region having first conductivity type and disposed to face itself with a first recess interposed therebetween, when viewed in a cross section along the thickness direction; and a body region having second conductivity type and disposed to face itself with the first recess interposed therebetween. Portions of the source region facing each other are connected to each other in a region interposed between the first recess and another first recess adjacent to the first recess, when viewed in a plan view.

Abstract: A silicon carbide substrate includes a first layer of a first conductivity type, a second layer of a second conductivity type provided on the first layer, and a third layer provided on the second layer and doped with an impurity for providing the first conductivity type. The silicon carbide substrate has a trench formed through the third layer and the second layer to reach the first layer. The first layer has a concentration peak of the impurity in a position away from the trench in the first layer. As a result, a silicon carbide semiconductor device having an electric field relaxation structure that can be readily formed is provided.

Abstract: A silicon carbide substrate includes: an n type drift layer having a first surface and a second surface opposite to each other; a p type body region provided in the first surface of the n type drift layer; and an n type emitter region provided on the p type body region and separated from the n type drift layer by the p type body region. A gate insulating film is provided on the p type body region so as to connect the n type drift layer and the n type emitter region to each other. A p type Si collector layer is directly provided on the silicon carbide substrate to face the second surface of the n type drift layer.

Abstract: A first drift layer has a first surface facing a first electrode and electrically connected to a first electrode, and a second surface opposite to the first surface. The first drift layer has an impurity concentration NA. A relaxation region is provided in a portion of the second surface of the first drift layer. The first drift layer and the second drift layer form a drift region in which the relaxation region is buried. The second drift layer has an impurity concentration NB, NB>NA being satisfied. A body region, a source region, and a second electrode are provided on the second drift layer.

Abstract: A silicon carbide semiconductor device includes an insulation film, and a silicon carbide layer having a surface covered with the insulation film. The surface includes a first region. The first region has a first plane orientation at least partially. The first plane orientation is any of a (0-33-8) plane, (30-3-8) plane, (-330-8) plane, (03-3-8) plane, (-303-8) plane, and (3-30-8) plane.

Abstract: A MOSFET includes: a substrate made of silicon carbide and having a first trench and a second trench formed therein, the first trench having an opening at the main surface side, the second trench having an opening at the main surface side and being shallower than the first trench; a gate insulating film; a gate electrode; and a source electrode disposed on and in contact with a wall surface of the second trench. The substrate includes a source region, a body region, and a drift region. The first trench is formed to extend through the source region and the body region and reach the drift region. The second trench is formed to extend through the source region and reach the body region.

Abstract: A MOSFET includes: a substrate provided with a trench having a side wall surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; an oxide film; and a gate electrode. The substrate includes a source region, a body region, and a drift region formed to sandwich the body region between the source region and the drift region. The source region and the body region are formed by means of ion implantation. The body region has an internal region sandwiched between the source region and the drift region and having a thickness of 1 ?m or smaller in a direction perpendicular to a main surface thereof. The body region has an impurity concentration of 3×1017 cm?3 or greater.

Abstract: A substrate has a surface made of a semiconductor having a hexagonal single-crystal structure of polytype 4H. The surface of the substrate is constructed by alternately providing a first plane having a plane orientation of (0-33-8), and a second plane connected to the first plane and having a plane orientation different from the plane orientation of the first plane. A gate insulating film is provided on the surface of the substrate. A gate electrode is provided on the gate insulating film.

Abstract: A drift layer forms a first main surface of a silicon carbide layer and has a first conductivity type. A source region is provided to be spaced apart from the drift layer by a body region, forms a second main surface, and has the first conductivity type. A relaxing region is provided within the drift layer and has a distance Ld from the first main surface. The relaxing region has a second conductivity type and has an impurity dose amount Drx. The drift layer has an impurity concentration Nd between the first main surface and the relaxing region. Relation of Drx>Ld·Nd is satisfied. Thus, a silicon carbide semiconductor device having a high breakdown voltage is provided.