Abstract: Each of first to third impurity regions of a silicon carbide substrate has a portion located on a flat surface of a first main surface. On the flat surface, a gate insulating film connects the first and third impurity regions to each other. On the flat surface, a first main electrode is in contact with the third impurity region. A second main electrode is provided on a second main surface. A side wall insulating film covers a side wall surface of the first main surface. The side wall surface is inclined by not less than 50° and not more than 80° relative to a {000-1} plane. In this way, a leakage current is suppressed in a silicon carbide semiconductor device.

Abstract: A MOSFET includes a silicon carbide substrate including a main surface having an off angle with respect to a {0001} plane and a source electrode formed in contact with the main surface. A base surface is exposed at at least a part of a contact interface of the silicon carbide substrate with the source electrode. With such a construction, the MOSFET achieves suppressed variation in threshold voltage.

Abstract: A silicon carbide film includes a first range having a first breakdown voltage holding layer, a charge compensation region, a first junction terminal region, and a first guard ring region. The silicon carbide film includes a second range having a second breakdown voltage holding layer, a channel forming region, and a source region. The first and second breakdown voltage holding layers constitutes a breakdown voltage holding region having a thickness in an element portion. When voltage is applied to attain a maximum electric field strength of 0.4 MV/cm or more in the breakdown voltage holding region during an OFF state, a maximum electric field strength in the second range within the element portion is configured to be less than ? of a maximum electric field strength in the first range.

Abstract: A silicon carbide semiconductor device includes a silicon carbide layer, an element region including a semiconductor element portion formed in the silicon carbide layer, a JTE region (first electric field relaxing region), an insulating film disposed on a first main surface and covering the JTE region, and a pad electrode electrically connected to the JTE region. The pad electrode includes an extension portion extending from an end of the JTE region close to the element region in a peripheral direction from the element region toward the JTE region, the extension portion being disposed on the insulating film. The extension portion overlies at least a portion of the JTE region.

Abstract: A method for manufacturing a silicon carbide semiconductor device includes the following steps. A silicon carbide substrate is prepared. A first heating step of heating the silicon carbide substrate in an atmosphere of oxygen is performed. A second heating step of heating the silicon carbide substrate to a temperature of 1300° C. or more and 1500° C. or less in an atmosphere of gas containing nitrogen atoms or phosphorus atoms is performed after the first heating step. A third heating step of heating the silicon carbide substrate in an atmosphere of a first inert gas is performed after the second heating step. Thus, the silicon carbide semiconductor device in which threshold voltage variation is small, and a method for manufacturing the same can be provided.

Abstract: A method of manufacturing an SiC semiconductor device includes the steps of forming a first oxide film on a first surface of an SiC semiconductor, removing the first oxide film, and forming a second oxide film constituting the SiC semiconductor device on a second surface exposed as a result of removal of the first oxide film in the SiC semiconductor. Between the step of removing the first oxide film and the step of forming a second oxide film, the SiC semiconductor is arranged in an atmosphere cut off from an ambient atmosphere.

Abstract: A MOSFET includes a semiconductor substrate having a trench formed in a main surface, a gate oxide film, a gate electrode, and a source interconnection. A semiconductor substrate includes an n-type drift layer and a p-type body layer. The trench is formed to penetrate the body layer and to reach the drift layer. The trench includes an outer peripheral trench arranged to surround an active region when viewed two-dimensionally. On the main surface opposite to the active region when viewed from the outer peripheral trench, a potential fixing region where the body layer is exposed is formed. The source interconnection is arranged to lie over the active region when viewed two-dimensionally. The potential fixing region is electrically connected to the source interconnection.

Abstract: A silicon carbide layer is epitaxially formed on a main surface of a substrate. The silicon carbide layer is provided with a trench having a side wall inclined relative to the main surface. The side wall has an off angle of not less than 50° and not more than 65° relative to a {0001} plane. A gate insulating film is provided on the side wall of the silicon carbide layer. The silicon carbide layer includes: a body region having a first conductivity type and facing a gate electrode with the gate insulating film being interposed therebetween; and a pair of regions separated from each other by the body region and having a second conductivity type. The body region has an impurity density of 5×1016 cm?3 or greater. This allows for an increased degree of freedom in setting a threshold voltage while suppressing decrease of channel mobility.

Abstract: A silicon carbide semiconductor device includes a silicon carbide layer, a body region, a source region, a gate insulating film, a gate electrode, a source electrode, a first impurity region, and a second impurity region. The second impurity region is disposed within the silicon carbide layer so as to connect the body region and the first impurity region to each other, and has a second conductivity type. An impurity concentration in the second impurity region is equal to or higher than an impurity concentration in the silicon carbide layer and equal to or lower than a lower limit of an impurity concentration in the body region.

Abstract: A silicon carbide substrate including a first impurity region, a well region, and a second impurity region separated from the first impurity region by the well region is prepared. A silicon dioxide layer is formed in contact with the first impurity region and the well region. A gate electrode is formed on the silicon dioxide layer. A silicon-containing material is formed on the first impurity region. The silicon-containing material is oxidized. The silicon dioxide layer includes a first silicon dioxide region on the first impurity region and a second silicon dioxide region on the well region. The thickness of the first silicon dioxide region is greater than the thickness of the second silicon dioxide region. Consequently, a silicon carbide semiconductor device capable of achieving improved switching characteristics while suppressing a decrease in drain current, and a method of manufacturing the same can be provided.

Abstract: A silicon carbide semiconductor device has a silicon carbide substrate, a gate insulating film, and a gate electrode. Silicon carbide substrate includes a first impurity region having a first conductivity type, a well region being in contact with the first impurity region and having a second conductivity type which is different from the first conductivity type, and a second impurity region separated from the first impurity region by the well region and having the first conductivity type. The gate insulating film is in contact with the first impurity region and the well region. The gate electrode is in contact with the gate insulating film and is arranged opposite to the well region with respect to the gate insulating film. A specific on-resistance at a voltage which is half a gate driving voltage applied to the gate electrode is smaller than twice the specific on-resistance at the gate driving voltage.

Abstract: A silicon carbide semiconductor device includes a silicon carbide layer, a body region, a source region, a gate insulating film, a gate electrode, a source electrode, a first impurity region, and a second impurity region. The second impurity region is disposed within the silicon carbide layer so as to connect the body region and the first impurity region to each other, and has a second conductivity type. An impurity concentration in the second impurity region is equal to or higher than an impurity concentration in the silicon carbide layer and equal to or lower than a lower limit of an impurity concentration in the body region.

Abstract: A first main surface of a silicon carbide substrate has a flat surface located in an element portion and a side wall surface located in a termination portion. The silicon carbide substrate has an impurity layer having a portion located at each of the flat surface of the first main surface and a second main surface. On the flat surface, a Schottky electrode is in contact with the impurity layer. On the second main surface, a counter electrode is in contact with the impurity layer. An insulating film covers the side wall surface. The side wall surface is inclined by not less than 50° and not more than 80° relative to a {000-1} plane. This suppresses the leakage current of a silicon carbide semiconductor device.

Abstract: A first portion of a silicon carbide substrate having an impurity of a first conductivity type is disposed deeper than a first depth position. A second portion is disposed to extend from the first depth position to a second depth position shallower than the first depth position. A third portion is disposed to extend from the second depth position to a main surface. The second portion has a second impurity concentration higher than a first impurity concentration of the first portion. The third portion has a third impurity concentration not less than the first impurity concentration and less than the second impurity concentration. A body region having an impurity of a second conductivity type has an impurity concentration peak at a depth position shallower than the first depth position and deeper than the second depth position.

Abstract: A silicon carbide substrate includes: an n type drift layer having a first surface and a second surface opposite to each other; a p type body region provided in the first surface of the n type drift layer; and an n type emitter region provided on the p type body region and separated from the n type drift layer by the p type body region. A gate insulating film is provided on the p type body region so as to connect the n type drift layer and the n type emitter region to each other. A p type Si collector layer is directly provided on the silicon carbide substrate to face the second surface of the n type drift layer.

Abstract: Each of first to third impurity regions of a silicon carbide substrate has a portion located on a flat surface of a first main surface. On the flat surface, a gate insulating film connects the first and third impurity regions to each other. On the flat surface, a first main electrode is in contact with the third impurity region. A second main electrode is provided on a second main surface. A side wall insulating film covers a side wall surface of the first main surface. The side wall surface is inclined by not less than 50° and not more than 80° relative to a {000-1} plane. In this way, a leakage current is suppressed in a silicon carbide semiconductor device.

Abstract: A method for manufacturing a silicon carbide semiconductor device includes the following steps. A silicon carbide substrate is prepared. A first heating step of heating the silicon carbide substrate in an atmosphere of oxygen is performed. A second heating step of heating the silicon carbide substrate to a temperature of 1300° C. or more and 1500° C. or less in an atmosphere of gas containing nitrogen atoms or phosphorus atoms is performed after the first heating step. A third heating step of heating the silicon carbide substrate in an atmosphere of a first inert gas is performed after the second heating step. Thus, the silicon carbide semiconductor device in which threshold voltage variation is small, and a method for manufacturing the same can be provided.

Abstract: A silicon carbide substrate includes a first impurity region, a well region in contact with the first impurity region, and a second impurity region separated from the first impurity region by the well region. A first main surface includes a first region in contact with a channel region, and a second region different from the first region. A silicon-containing material is formed on the second region. A first silicon dioxide region is formed on the first region. A second silicon dioxide region is formed by oxidizing the silicon-containing material. A gate runner is electrically connected to a gate electrode and formed in a position facing the second silicon dioxide region. Consequently, a silicon carbide semiconductor device capable of achieving improved insulation performance between the gate runner and the substrate while the surface roughness of the substrate is suppressed, and a method of manufacturing the same can be provided.

Abstract: A MOSFET includes: a substrate having a first trench formed therein, the first trench opening on a side of one main surface; a gate insulating film; and a gate electrode. The substrate includes an n type source region, a p type body region, an n type drift region, and a p type deep region making contact with the body region and extending to a region deeper than the first trench. The first trench is formed such that a distance between the wall surface and the deep region increases with increasing distance from the main surface of the substrate.

Abstract: A silicon carbide semiconductor device includes an element region and a guard ring region. A semiconductor element is provided in the element region. The guard ring region surrounds the element region in a plan view and has a first conductivity type. The semiconductor element includes a drift region having a second conductivity type different from the first conductivity type. The guard ring region includes a linear region and a curvature region continuously connected to the linear region. A value obtained by dividing a radius of curvature of an inner circumference portion of the curvature region by a thickness of the drift region is not less than 5 and not more than 10. Accordingly, there can be provided a silicon carbide semiconductor device capable of improving a breakdown voltage while suppressing decrease of on-state current.