Abstract: Disclosed is a semiconductor device having a delay adjusting circuit including a delay line having N stages of differential delay circuits and N stages of differential interpolators. A differential interpolator of an Mth (where M<N holds) stage receives an output signal of a differential delay circuit of the Mth stage and an output signal of a differential interpolator of an (M+1)th stage. A differential amplifier of an Nth stage receives an output signal of a differential delay circuit of the Nth stage as an input and synthesizes this signal into a signal with a synthesizing ratio of 100%. One differential interpolator from among differential interpolators from first to (N?1)th stages performs waveform synthesis over a range of 0% to 100% in accordance with an analog control signal from a digital-to-analog converter. The output of the differential interpolator of the first stage becomes an output signal, the delay of which has been adjusted.

Abstract: A semiconductor storage device includes a memory array compartmentalized into first and second regions alternately arranged. The second regions are formed by odd and even columns alternately arranged. The semiconductor storage device includes: a memory mat array arranged in each first region; a sense amp array arranged in each second region; local IO lines arranged in each second region and connected to the sense amp array; main IO lines crossing the first and second regions; and a read/write amplifier arranged in each second region and at an intersection region where the local IO lines cross the main IO lines. The read/write amplifier in an odd column is connected to a local IO line therein and to a local IO line in the next odd column. The read/write amplifier in an even column is connected to a local 10 line therein and to a local IO line in the next even column.

Abstract: In order to solve the problem in that information relating to a specific purpose can be saved in the internal memory of a mobile apparatus on which a permanent memory is mounted while information relating to other purpose cannot be saved in the internal memory of the apparatus, the purpose of each telephone call is distinguished by sending a non-telephone type notice before transferring the call and thus the user can determine whether the call should be saved or not.

Abstract: First and second reference-potential generator units output first and second reference potentials V1 and V7, respectively, which correspond to first and second specific temperatures to be detected. An intermediate-potentials generator unit divides the potential difference between the reference potential V1 and the reference potential V7 to output intermediate potentials through nodes N2 to N6. A temperature-dependant-potential generator unit outputs the forward voltage drop of a diode which varies depending on the ambient temperature. A comparator compares one of the potentials of nodes N1 to N7 selected by a selector against the potential output by the temperature-dependant-potential generator unit and outputs the result of the comparison indicating the range of the ambient temperature.

Abstract: A PLL circuit includes a phase comparator for outputting a frequency control signal based on a result of comparison between phases of an input reference clock signal and a fed-back oscillation signal; an oscillation circuit, connected to the phase comparator, for outputting an oscillation signal having a frequency in accordance with the frequency control signal, a power source voltage, and a predetermined reference voltage; and a bias control circuit, connected to the oscillation circuit, for increasing either the potential difference between the reference voltage of the oscillation circuit and a ground voltage or the potential difference between the power source voltage of the oscillation circuit and the ground voltage. A transistor in the oscillation circuit can operate in a saturation area, thereby operating the PLL circuit at a high speed with a low power source voltage, without being easily affected by a variation in the temperature or other process conditions.

Abstract: A delay circuit has a circuit structure dominated by an NMOS or a PMOS transistor. The delay circuit is supplied with, as a power supply voltage, an output voltage of a power supply voltage step-down circuit having a level generating circuit for generating a reference voltage obtained by an offset voltage and a manufacturing variation dependent voltage, and an m-time voltage generating circuit. A semiconductor device includes the delay circuit.

Abstract: Input circuits connected to an external input terminal PAD via resistor elements are activated in response to the level transition of the clock signals supplied thereto for accepting input signals. In order to input signals applied to the external input terminal PAD clock signals having different phases are supplied to the respective input circuits. The cycle time of each one input circuit can be made longer by sequentially assigning the serial data supplied to the external input terminals in response to the clock signals having different clock signals. Since the input circuits are isolated from each other by means of the resistor elements, the influence of the kick back signal which occurs at first stage of each the input circuit upon the other input circuit can be made very small.

Abstract: A semiconductor memory device includes: a command latch circuit that latches a command signal; an address latch circuit that latches an address signal; a mode latch circuit that latches a mode signal; and a command decoder that selects the address latch circuit in response to the latch of a normal command by the command latch circuit, and selects the mode latch circuit in response to the latch of an adjustment command. With this arrangement, the mode signal can be dynamically received without performing a mode register set. Therefore, when a sufficiently large latch margin of the mode latch circuit is secured, there is no risk that it becomes impossible to input the mode signal.

Abstract: Input circuits connected to an external input terminal PAD via resistor elements are activated in response to the level transition of the clock signals supplied thereto for accepting input signals. In order to input signals applied to the external input terminal PAD clock signals having different phases are supplied to the respective input circuits. The cycle time of each one input circuit can be made longer by sequentially assigning the serial data supplied to the external input terminals in response to the clock signals having different clock signals. Since the input circuits are isolated from each other by means of the resistor elements, the influence of the kick back signal which occurs at first stage of each the input circuit upon the other input circuit can be made very small.

Abstract: A semiconductor memory device performs a refresh operation sequentially for a word line selected based on a row address when receiving a refresh request, and comprises: a memory cell array divided into M banks; a refresh counter for sequentially outputting a count value corresponding to the word line to be refreshed in response to the refresh request; and a row address converter for supplying row addresses different from one anther in at lest two banks among the M banks by converting the count value. In the semiconductor memory device, a predetermined number of selected word lines are refreshed at the same time in the banks in accordance with different patterns from one another, and the maximum value of the total number of the selected word lines refreshed at the same time for all the M banks is controlled to be lower than 2M.

Abstract: A DLL circuit has a rise delay adjustment circuit and a fall delay adjustment circuit. The fall delay adjustment circuit is supplied with a clock adjusted on a rise side in the rise delay adjustment circuit. Since the clock supplied to the fall delay adjustment circuit has already been adjusted on the rise side, a delay difference on a fall side is very small. Therefore, the fall delay adjustment circuit and a fall counter can be drastically reduced in circuit scale. As a consequence, it is possible to obtain the DLL circuit having a small circuit scale and high accuracy.

Abstract: An apparatus a counter, storage units for storing count values interrupted by a row address whose refresh period is subject to change; comparator circuits for comparing the counter outputs and the contents of the storage units to each other as to whether or not the counter outputs coincide with the contents of the storage units; a holding circuit for setting an output hit signal to an active state when a coincidence signal is output from the comparator circuits and for resetting the hit signal to an inactive state in the next following clock cycle; a circuit performing control for not propagating a refresh clock signal to the counter when the hit signal is in an active state and for propagating the refresh clock signal to the counter when the hit signal is in an inactive state; a circuit for replacing an output of the counter by a row address which changes part of the counter output when the hit signal is in an activate state to replace the counter output with the row address whose refresh period is subject t

Abstract: A data transmission system including a slave device (30) and a master device (10) is disclosed. Slave device (30) may include a slave side clock signal generator section (32) for generating a slave side clock signal (CLKSOUT), a phase adjusting circuit (40) for controlling a phase of a slave side clock signal (CLKSOUT), output sections (33-1 to 33-m) for outputting transmission data signals (SD1 to SDm) in response to slave side clock signal (CLKSOUT), and a timing reference signal generator section (34) for outputting a timing reference signal (SSPH) in response to slave side clock signal (CLKSOUT).

Abstract: A data transmission system including a slave device (30) and a master device (10) is disclosed. Slave device (30) may include a slave side clock signal generator section (32) for generating a slave side clock signal (CLKSOUT), a phase adjusting circuit (40) for controlling a phase of a slave side clock signal (CLKSOUT), output sections (33-1 to 33-m) for outputting transmission data signals (SD1 to SDm) in response to slave side clock signal (CLKSOUT), and a timing reference signal generator section (34) for outputting a timing reference signal (SSPH) in response to slave side clock signal (CLKSOUT).

Abstract: A pulse generation section generates a pulse which is at H-level for the predetermined period of time from the timing of the input signal DATA changing to L-level. A main output section outputs a signal of L-level with transistors P1, N1, and N2 turned ON, while the pulse generation section outputs a pulse. When the pulse falls, the transistors P1 and N1 are turned OFF, and a potential of an output node is held at L-level by resistors of a L-level holding section.

Abstract: Using a swirl type fuel injection valve, a concentrated spray area and a thin spray area are formed, the positions thereof are adjusted, and the spray is made to conform to the geometric shape of the engine and mounting position of the fuel injection valve, so as to reduce the fuel consumption and control the unburnt components in exhaust gas. The fuel injection valve is so constructed that a step is formed on the injection hole opening of the fuel injection valve, so as to provide two or more edge transition portions at the injection hole opening, resulting from the step, and the line connecting the edge transition portions forms an oblique angle relative to the wall formed by the step perpendicular to the injection hole center axis and the angled wall.

Abstract: First and second reference-potential generator units output first and second reference potentials V1 and V7, respectively, which correspond to first and second specific temperatures to be detected. An intermediate-potentials generator unit divides the potential difference between the reference potential V1 and the reference potential V7 to output intermediate potentials through nodes N2 to N6. A temperature-dependant-potential generator unit outputs the forward voltage drop of a diode which varies depending on the ambient temperature. A comparator compares one of the potentials of nodes N1 to N7 selected by a selector against the potential output by the temperature-dependant-potential generator unit and outputs the result of the comparison indicating the range of the ambient temperature.

Abstract: Three flip-flops receive a common data signal input through a data terminal based on different timing signals which are obtained from an external timing signal and differ from one another by a specific delay step. A judging circuit judges whether or not the output data of the three flip-flops coincide with one another. If all the output data coincide with one another, the latch timing is maintained, whereas if the output data of the flip-flop latching the data signal at a fastest or latest timing differs from the output data of the flip-flop latching the data signal at the central timing, the judging circuit changes the variable timing to obtain a suitable latch timing.

Abstract: An apparatus a counter, storage units for storing count values interrupted by a row address whose refresh period is subject to change; comparator circuits for comparing the counter outputs and the contents of the storage units to each other as to whether or not the counter outputs coincide with the contents of the storage units; a holding circuit for setting an output hit signal to an active state when a coincidence signal is output from the comparator circuits and for resetting the hit signal to an inactive state in the next following clock cycle; a circuit performing control for not propagating a refresh clock signal to the counter when the hit signal is in an active state and for propagating the refresh clock signal to the counter when the hit signal is in an inactive state; a circuit for replacing an output of the counter by a row address which changes part of the counter output when the hit signal is in an activate state to replace the counter output with the row address whose refresh period is subject t

Abstract: In order to compare a phase of an internal clock signal outputted from a clock driver with that of a data strobe signal from a data strobe output circuit driven by the internal clock signal, a selector is disposed to supply a data strobe signal instead of an external clock signal inputted into a phase comparison circuit. While the selector selects the data strobe signal, the selector, a replica circuit, and the phase comparison circuit operate as a phase advance/delay signal generation circuit to output a phase advance/delay signal indicating a timing deviation to an external output terminal.