Abstract: A semiconductor device includes a first input buffer adjusting a logic threshold voltage, a first replica circuit, a first reference voltage generating circuit, and a first comparator circuit. The first replica circuit is identical in circuit configuration to the first input buffer. The first replica circuit has an input and an output connected to the input. The first replica circuit generates the logic threshold voltage as an output voltage. The first reference voltage generating circuit generates a first reference voltage. The first comparator circuit compares the logic threshold voltage as an output voltage of the first replica circuit to the first reference voltage to generate a first threshold adjustment signal. The first comparator circuit supplies the first threshold adjustment signal to the first input buffer and the first replica circuit. The first threshold adjustment signal allows the first input buffer to adjust the logic threshold voltage.

Abstract: A semiconductor device that includes a semiconductor substrate. First and second mode registers are provided on the semiconductor substrate and store information, respectively. First and second circuits are provided on the semiconductor substrate. The first and second circuits have substantially the same configuration. The first and second circuits perform an operation in response to the information of the first and second mode registers, respectively.

Abstract: A memory system includes a clock generation circuit, a memory device, and a controller. The memory device includes output circuits and a temperature sensor, the output circuits configured to output data at an output timing obtained based on a clock signal supplied from the clock generation circuit. The controller includes input circuits that receive the data outputted from the memory device at an input timing obtained based on a clock signal supplied from the clock generation circuit and a correction value setting circuit that adjusts the input timing based on a temperature value from the temperature sensor.

Abstract: A memory system includes a plurality of memory devices having data terminals that are commonly connected to a memory controller. Each of the memory devices includes a data output circuit that outputs read data that is read from a memory cell array in response to a read command to the data terminal, and an output-timing adjustment circuit that adjusts an output timing of read data that is output from the data output circuit. The memory controller sets an adjustment amount of adjustment performed by an output-timing adjustment circuit such that delay times from when the read command is issued until when the read data is received match in the memory devices, by issuing a setting command to each of the memory devices.

Abstract: A memory system includes a plurality of memory devices having data terminals that are commonly connected to a memory controller. Each of the memory devices includes a data output circuit that outputs read data that is read from a memory cell array in response to a read command to the data terminal, and an output-timing adjustment circuit that adjusts an output timing of read data that is output from the data output circuit. The memory controller sets an adjustment amount of adjustment performed by an output-timing adjustment circuit such that delay times from when the read command is issued until when the read data is received match in the memory devices, by issuing a setting command to each of the memory devices.

Abstract: Disclosed herein is a device that includes: a data terminal; a plurality of memory banks; and a control circuit configured to control a data transfer between the data terminal and the memory banks. The control circuit is configured to set a read latency in response to a burst length.

Abstract: A semiconductor device includes a first input buffer adjusting a logic threshold voltage, a first replica circuit, a first reference voltage generating circuit, and a first comparator circuit. The first replica circuit is identical in circuit configuration to the first input buffer. The first replica circuit has an input and an output connected to the input. The first replica circuit generates the logic threshold voltage as an output voltage. The first reference voltage generating circuit generates a first reference voltage. The first comparator circuit compares the logic threshold voltage as an output voltage of the first replica circuit to the first reference voltage to generate a first threshold adjustment signal. The first comparator circuit supplies the first threshold adjustment signal to the first input buffer and the first replica circuit. The first threshold adjustment signal allows the first input buffer to adjust the logic threshold voltage.

Abstract: A memory system includes a plurality of memory devices having data terminals that are commonly connected to a memory controller. Each of the memory devices includes a data output circuit that outputs read data that is read from a memory cell array in response to a read command to the data terminal, and an output-timing adjustment circuit that adjusts an output timing of read data that is output from the data output circuit. The memory controller sets an adjustment amount of adjustment performed by an output-timing adjustment circuit such that delay times from when the read command is issued until when the read data is received match in the memory devices, by issuing a setting command to each of the memory devices.

Abstract: An electromagnetic fuel injection valve includes: a valve element which closes a fuel passage by coming into contact with a valve seat and opens the fuel passage by going away from the valve seat; an electromagnet which includes a coil and a magnetic core formed as a drive portion for driving the valve element; a movable element which is held by the valve element in a state where the movable element is displaceable in the direction of a drive force of the valve element relative to the valve element; a first biasing portion for biasing the valve element in the direction opposite to the direction of a drive force generated by the drive portion; a second biasing portion for biasing the movable element in the direction of the drive force with a biasing force smaller than the biasing force generated by the first biasing portion; and a restricting portion for restricting the displacement of the movable element in the direction of the drive force relative to the valve element.

Abstract: In a semiconductor device in which semiconductor chips having a number of signal TSVs are stacked, a huge amount of man-hours have been required to perform a continuity test for each of the signal TSVs. According to the present invention, no continuity test is performed directly on signal TSVs. Dummy bumps are arranged in addition to signal TSVs. The dummy bumps of the semiconductor chips are connected through a conduction path that can pass the dummy bumps between the semiconductor chips with one stroke when the semiconductor chips are stacked. A continuity test of the conduction path allows a bonding defect on bonded surfaces of two of the stacked semiconductor chips to be measured and detected.

Abstract: The present invention is applicable to a semiconductor device having a plurality of chips being stacked with a TSV structure in which adjacent ones of the chips are connected to each other via a plurality of through electrodes. Each of the chips includes a plurality of TSV array portions provided so as to correspond to a plurality of channels. The TSV array portions include a TSV array portion that contributes to an input and an output depending upon the number of the chips being stacked, and a pass-through TSV array portion that is not connected to an input/output circuit.

Abstract: A system including a controller and a memory chip. The controller includes first and second selection signal terminals supplying first and second selection signals, respectively, multiple first data terminals and multiple second data terminals. The memory chip includes a semiconductor substrate, third and fourth selection signal terminals provided on the semiconductor substrate and electrically coupled to the first and second selection signal terminals of the controller, respectively. Multiple third data terminals are provided on the semiconductor substrate and electrically coupled to the first data terminals of the controller, respectively. Multiple fourth data terminals are provided on the semiconductor substrate and electrically coupled to the second data terminals of the controller, respectively. The first and third data terminals communicate first data in response to the first selection signal. The second and fourth data terminals communicate second data in response to the second selection signal.

Abstract: A semiconductor device that includes a semiconductor substrate. First and second mode registers are provided on the semiconductor substrate and store information, respectively. First and second circuits are provided on the semiconductor substrate. The first and second circuits have substantially the same configuration. The first and second circuits perform an operation in response to the information of the first and second mode registers, respectively.

Abstract: A device includes a semiconductor substrate, a first penetrating electrode penetrating through the semiconductor substrate, a first test pad, and a first tri-state buffer coupled between the first penetrating electrode and the first test pad. The first tri-state buffer receives a buffer control signal at a control terminal thereof. The device further includes a buffer control circuit supplying the buffer control signal to the first tri-state buffer.

Abstract: A device includes a semiconductor substrate, a first penetration electrode and a plurality of second penetration electrodes each penetrating the semiconductor substrate, a first terminal and a plurality of second terminals formed on a one side of the substrate, and a third terminal and a plurality of fourth terminals formed on an opposite side of the substrate. Each of the first and third terminals is vertically aligned with and electrically connected to first penetration electrode. Each of the second terminals is vertically aligned with an associated one of the second penetration electrodes and electrically connected to another one of the second penetration terminals that is not vertically aligned with the associated second terminal. Each of fourth terminals is vertically aligned with and electrically connected to an associated one of the second penetration electrodes.

Abstract: A semiconductor device includes a first circuit, a second circuit, and a first voltage dividing circuit. The first circuit is coupled to a first terminal. The first circuit is operable by a first voltage supplied from the first terminal. The second circuit is coupled through a first resistive element to the first terminal. The second circuit is operable by a second voltage supplied through the first resistive element from the first terminal. The second voltage is smaller in absolute value than the first voltage. The first voltage dividing circuit is coupled to a first node between the first resistive element and the second circuit. The first voltage dividing circuit has a conductive state and a non-conductive state. The first voltage dividing circuit is kept in the conductive state while applying the first voltage to the first terminal to allow the first circuit to operate by the first voltage.

Abstract: Disclosed herein is a device that includes a plurality of memory circuits and a refresh control circuit configured to generate a plurality of refresh initiation signals such that one of the refresh initiation signals takes an active level. Each of the memory circuits comprises a memory cell array including a plurality of memory cells, at least one data terminal, a data read/write circuit performing a data read operation to read out read-data from a selected one of the memory cells and supply the read-data to the data terminal and a data write operation to receive write-data from the data terminal and write the write-data into a selected one of the memory cells, and a refresh circuit performing a data refresh operation on selected one or ones of the memory cells of the memory cell array in response to an associated one of the refresh initiation signals taking the active level.

Abstract: To include first and second data input/output terminals allocated to first and second memory circuit units, respectively, and an address terminal allocated in common to these memory circuit units. When a first chip selection signal is activated, the first memory circuit unit performs a read operation or a write operation via the first data input/output terminal based on an address signal regardless of an operation of the second memory circuit unit. When a second chip selection signal is activated, the second memory circuit unit performs a read operation or a write operation via the second data input/output terminal based on the address signal regardless of an operation of the first memory circuit unit. With this configuration, a wasteful data transfer can be prevented, and the effective data transfer rate can be increased.

Abstract: In a fuel injection valve used for an internal combustion engine, a valve closing lag time due to fluid resistance in a fuel path is shortened to decrease a minimum injection limit. More specifically, in the fuel injection valve in which an anchor is attracted to an end face part of a stationary core having a fuel path formed at a center part thereof by means of electromagnetic force, and in which a fuel injection hole is opened and closed by controlling a valve disc driven in conjunction with the anchor, there are provided a fuel reservoir part at a center part of an upper end face part of the anchor, a through hole extending axially in a fashion that an end part thereof is open to the fuel reservoir part, and a fuel path extending radially outward from the fuel reservoir part so that fuel is fed to a magnetic attraction gap between an upper end face part of the anchor and a lower end face part of the stationary core.

Abstract: A device includes: a first substrate including a plurality of first electrodes; a plurality of chips each including a plurality of through electrodes, the chips being stacked with each other such that the through electrodes of a lower one of the chips are connected respectively the through electrodes of an upper one of the chips to provide a chip stacked body; and a second substrate cooperating the first substrate to sandwich the chip stacked body between the first and second substrates, the second substrate including a plurality of second electrodes on a first surface that is opposite to a second surface facing the chip stacked body, each of the second electrodes being electrically connected to an associated one of the through electrodes of an uppermost one of the chips of the chip stacked body.