Abstract: A device includes a control circuit that triggers a first operation every time a specific signal is supplied thereto, and that triggers a second operation in place of the first operation in response to the first specific signal supplied after the number of the first operation performed has reached a predetermined number.

Abstract: Disclosed herein is a method for manufacturing a tested apparatus that includes forming a stacked structure that includes a plurality of first semiconductor chips stacked over a semiconductor wafer. The semiconductor wafer comprises a plurality of second semiconductor chips that are arranged in matrix of a plurality of rows and columns. Each of the first semiconductor chips is stacked over and electrically connected to a different one of the second semiconductor chips. The method further includes contacting a probe card to at least one of the first semiconductor chips to perform a first test operation on a corresponding one of the second semiconductor chips with an intervention of the at least one of the first semiconductor chips so that a plurality of tested apparatus each comprising a pair of first and second semiconductor chips stacked with each other is derived.

Abstract: A memory system includes a plurality of memory devices having data terminals that are commonly connected to a memory controller. Each of the memory devices includes a data output circuit that outputs read data that is read from a memory cell array in response to a read command to the data terminal, and an output-timing adjustment circuit that adjusts an output timing of read data that is output from the data output circuit. The memory controller sets an adjustment amount of adjustment performed by an output-timing adjustment circuit such that delay times from when the read command is issued until when the read data is received match in the memory devices, by issuing a setting command to each of the memory devices.

Abstract: Disclosed herein is a device that includes a first semiconductor chip. The first semiconductor chip includes a first data storage area storing data, a first refresh circuit repeating a first refresh operation on the first data storage area to make the first data storage area retain the data, a first terminal supplied with a first control signal from outside of the first semiconductor chip, and a first control circuit coupled between the first terminal and the first refresh circuit to control a repetition cycle of the first refresh operation in response to the first control signal.

Abstract: A memory system includes a plurality of memory devices having data terminals that are commonly connected to a memory controller. Each of the memory devices includes a data output circuit that outputs read data that is read from a memory cell array in response to a read command to the data terminal, and an output-timing adjustment circuit that adjusts an output timing of read data that is output from the data output circuit. The memory controller sets an adjustment amount of adjustment performed by an output-timing adjustment circuit such that delay times from when the read command is issued until when the read data is received match in the memory devices, by issuing a setting command to each of the memory devices.

Abstract: A device includes a semiconductor substrate, a first penetrating electrode penetrating through the semiconductor substrate, a first test pad, and a first tri-state buffer coupled between the first penetrating electrode and the first test pad. The first tri-state buffer receives a buffer control signal at a control terminal thereof. The device further includes a buffer control circuit supplying the buffer control signal to the first tri-state buffer.

Abstract: A semiconductor device includes a plurality of signal terminals on each of a plurality of vertically stacked semiconductor chips, each plurality of signal terminals connected to vertically aligned signal terminals of an adjacent semiconductor chip by through silicon vias, a common test terminal on each of the plurality of vertically stacked semiconductor chips connected to a vertically aligned common test terminal of an adjacent semiconductor chip by a through silicon via; a plurality of spiral test terminals on the plurality of vertically stacked semiconductor chips, each spiral test terminal connected to a non-vertically aligned spiral test terminal of an adjacent semiconductor chip by a through silicon via, and a conductive line arranged along a periphery of at least one of the plurality of vertically stacked semiconductor chips, the conductive line connected to a respective common test terminal and a respective spiral test terminal.

Abstract: A memory system includes a plurality of memory devices having data terminals that are commonly connected to a memory controller. Each of the memory devices includes a data output circuit that outputs read data that is read from a memory cell array in response to a read command to the data terminal, and an output-timing adjustment circuit that adjusts an output timing of read data that is output from the data output circuit. The memory controller sets an adjustment amount of adjustment performed by an output-timing adjustment circuit such that delay times from when the read command is issued until when the read data is received match in the memory devices, by issuing a setting command to each of the memory devices.

Abstract: A device includes a semiconductor substrate, a first penetrating electrode penetrating through the semiconductor substrate, a first test pad, and a first tri-state buffer coupled between the first penetrating electrode and the first test pad. The first tri-state buffer receives a buffer control signal at a control terminal thereof. The device further includes a buffer control circuit supplying the buffer control signal to the first tri-state buffer.

Abstract: A method for synchronizing an output clock signal with an input clock signal in a delay locked loop. A first count values decreasing the number of bypassed elements in a differential delay line until an edge of the output clock signal is delayed relative to an edge of the input clock signal or the first count value reaches a first count final value if the first count value reaches the first count final value, a second count value is adjusting to decrease the number of bypassed elements in a single-ended delay line until the edge of the output clock signal is delayed relative to the edge of the input clock signal. A third count value is adjusted to decrease the delay of an interpolator until the edge of the output clock signal is no longer delayed with respect to the edge of the input clock signal.

Abstract: A semiconductor device includes a plurality of signal terminals on each of a plurality of vertically stacked semiconductor chips, each plurality of signal terminals connected to vertically aligned signal terminals of an adjacent semiconductor chip by through silicon vias, a common test terminal on each of the plurality of vertically stacked semiconductor chips connected to a vertically aligned common test terminal of an adjacent semiconductor chip by a through silicon via; a plurality of spiral test terminals on the plurality of vertically stacked semiconductor chips, each spiral test terminal connected to a non-vertically aligned spiral test terminal of an adjacent semiconductor chip by a through silicon via, and a conductive line arranged along a periphery of at least one of the plurality of vertically stacked semiconductor chips, the conductive line connected to a respective common test terminal and a respective spiral test terminal.

Abstract: To provide a solid electrolytic capacitor having a high capacitance and an excellent heat resistance. A solid electrolytic capacitor includes: an anode 2; a dielectric layer 3 provided on the surface of the anode 2; a first conductive polymer layer 4a provided on the dielectric layer 3; a second conductive polymer layer 4b provided on the first conductive polymer layer 4a; a third conductive polymer layer 4c provided on the second conductive polymer layer 4b; and a cathode layer provided on the third conductive polymer layer 4c, wherein the first conductive polymer layer 4a is made of a conductive polymer film formed by polymerizing pyrrole or a derivative thereof, the second conductive polymer layer 4b is made of a conductive polymer film formed by polymerizing thiophene or a derivative thereof, and the third conductive polymer layer 4c is made of a conductive polymer film formed by electropolymerizing pyrrole or a derivative thereof.

Abstract: To include first and second data input/output terminals allocated to first and second memory circuit units, respectively, and an address terminal allocated in common to these memory circuit units. When a first chip selection signal is activated, the first memory circuit unit performs a read operation or a write operation via the first data input/output terminal based on an address signal regardless of an operation of the second memory circuit unit. When a second chip selection signal is activated, the second memory circuit unit performs a read operation or a write operation via the second data input/output terminal based on the address signal regardless of an operation of the first memory circuit unit. With this configuration, a wasteful data transfer can be prevented, and the effective data transfer rate can be increased.

Abstract: A semiconductor device is provided with: a delay circuit including a first delay unit that has a plurality of differential first delay elements which are respectively connected in series, a plurality pairs of first contacts which are respectively provided between the plurality of first delay elements, and a first output circuit that outputs a first delayed signal corresponding to a pair of first contacts selected from among the plurality pairs of first contacts, on receiving a first selection signal; a second delay unit that receives the first delayed signal, and that includes a plurality of single-ended second delay elements which are respectively connected in series, a plurality of second contacts which are respectively provided between the plurality of second delay elements, and a second output circuit that outputs a second delayed signal corresponding to a second contact selected from among the plurality of second contacts, on receiving a second selection signal; and a control circuit that outputs each of

Abstract: The present invention provides an electrode that can be used for a sodium secondary battery having a larger discharge capacity when charging and discharging are performed repeatedly than that of the prior art. This sodium secondary battery electrode contains tin (Sn) powder as an electrode active material. The electrode, particularly, further contains one or more electrode-forming agents selected from the group consisting of poly(vinylidene fluoride) (PVDF), poly(acrylic acid) (PAA), poly(sodium acrylate) (PAANa), and carboxymethylcellulose (CMC), thereby making it possible to provide a sodium secondary battery having even greater electrode performance.

Abstract: A memory system includes a plurality of memory devices having data terminals that are commonly connected to a memory controller. Each of the memory devices includes a data output circuit that outputs read data that is read from a memory cell array in response to a read command to the data terminal, and an output-timing adjustment circuit that adjusts an output timing of read data that is output from the data output circuit. The memory controller sets an adjustment amount of adjustment performed by an output-timing adjustment circuit such that delay times from when the read command is issued until when the read data is received match in the memory devices, by issuing a setting command to each of the memory devices.

Abstract: A system including a controller and a memory chip. The controller includes first and second selection signal terminals supplying first and second selection signals, respectively, multiple first data terminals and multiple second data terminals. The memory chip includes a semiconductor substrate, third and fourth selection signal terminals provided on the semiconductor substrate and electrically coupled to the first and second selection signal terminals of the controller, respectively. Multiple third data terminals are provided on the semiconductor substrate and electrically coupled to the first data terminals of the controller, respectively. Multiple fourth data terminals are provided on the semiconductor substrate and electrically coupled to the second data terminals of the controller, respectively. The first and third data terminals communicate first data in response to the first selection signal. The second and fourth data terminals communicate second data in response to the second selection signal.

Abstract: In order to solve the problem in that information relating to a specific purpose can be saved in the internal memory of a mobile apparatus on which a permanent memory is mounted while information relating to other purpose cannot be saved in the internal memory of the apparatus, the purpose of each telephone call is distinguished by sending a non-telephone type notice before transferring the call and thus the user can determine whether the call should be saved or not.

Abstract: An additive for a sodium ion secondary battery of the present invention includes a compound of at least one of a saturated cyclic carbonate having a fluoro group and a chain carbonate having a fluoro group. A sodium ion secondary battery (1) of the present invention includes: a non-aqueous electrolytic solution including the additive for a sodium ion secondary battery and a non-aqueous solvent containing a saturated cyclic carbonate or a non-aqueous solvent containing a saturated cyclic carbonate and a chain carbonate; a positive electrode (11); and a negative electrode (12) that includes a coating formed in a surface of the negative electrode, the coating containing a composite material having carbon, oxygen, fluorine and sodium in the surface and includes a negative-electrode active material containing a hard carbon.

Abstract: A device includes a semiconductor substrate, a first penetration electrode and a plurality of second penetration electrodes each penetrating the semiconductor substrate, a first terminal and a plurality of second terminals formed on a one side of the substrate, and a third terminal and a plurality of fourth terminals formed on an opposite side of the substrate. Each of the first and third terminals is vertically aligned with and electrically connected to first penetration electrode. Each of the second terminals is vertically aligned with an associated one of the second penetration electrodes and electrically connected to another one of the second penetration terminals that is not vertically aligned with the associated second terminal. Each of fourth terminals is vertically aligned with and electrically connected to an associated one of the second penetration electrodes.