Patents by Inventor Toshiaki Ishii

Toshiaki Ishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120104618
    Abstract: A bonding material comprising metal particles coated with an organic substance having carbon atoms of 2 to 8, wherein the metal particles comprises first portion of 100 nm or less, and a second portion larger than 100 nm but not larger than 100 ?m, each of the portions having at least peak of a particle distribution, based on a volumetric base. The disclosure is further concerned with a bonding method using the bonding material.
    Type: Application
    Filed: January 11, 2012
    Publication date: May 3, 2012
    Inventors: Yusuke Yasuda, Toshiaki Morita, Eiichi Ide, Hiroshi Hozoji, Toshiaki Ishii
  • Publication number: 20110204125
    Abstract: A bonding material comprising metal particles coated with an organic substance having carbon atoms of 2 to 8, wherein the metal particles comprises first portion of 100 nm or less, and a second portion larger than 100 nm but not larger than 100 ?m, each of the portions having at least peak of a particle distribution, based on a volumetric base. The disclosure is further concerned with a bonding method using the bonding material.
    Type: Application
    Filed: May 3, 2011
    Publication date: August 25, 2011
    Inventors: Yusuke YASUDA, Toshiaki MORITA, Eiichi IDE, Hiroshi HOZOJI, Toshiaki ISHII
  • Patent number: 7955411
    Abstract: A bonding material comprising metal particles coated with an organic substance having carbon atoms of 2 to 8, wherein the metal particles comprises first portion of 100 nm or less, and a second portion larger than 100 nm but not larger than 100 ?m, each of the portions having at least peak of a particle distribution, based on a volumetric base. The disclosure is further concerned with a bonding method using the bonding material.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: June 7, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Yusuke Yasuda, Toshiaki Morita, Eiichi Ide, Hiroshi Hozoji, Toshiaki Ishii
  • Publication number: 20110075334
    Abstract: An object of the present invention is to provide a mechanically and electrically integrated type electronic control apparatus which can be embedded in a compact mechanical part, and has a compact structure while having a high wiring freedom, a high heat dissipation and a high reliability. In a mechanically and electrically integrated type electronic control apparatus provided with a control signal generating part, and an angular wiring member connecting the control signal generating part and a controlled part controlled by a control signal of the control signal generating part, installed within a conductive casing, at least the wiring member has a fixed hole, a surface including the fixed hole is coated in an insulative manner, and the fixed hole is fixed to the conductive casing mechanically while keeping an insulating property.
    Type: Application
    Filed: July 7, 2010
    Publication date: March 31, 2011
    Applicant: Hitachi Automotive Systems, Ltd.
    Inventors: Nobutake TSUYUNO, Itaru TANABE, Toshiaki ISHII, Hiroshi KAMEYAMA
  • Patent number: 7816786
    Abstract: A semiconductor device includes a semiconductor chip and leads electrically connected to the electrodes of the semiconductor chip. A hollow radiator base houses the semiconductor device which is molded with high-thermal-conductivity resin having an electrical insulating property. The radiator base has a cooling-medium channel therein or radiating fins on the outside. Alternatively, the radiator base is housed in a second radiator base.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: October 19, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Kinya Nakatsu, Hideki Miyazaki, Yoshitaka Takezawa, Toshiaki Ishii, Hiroshi Hozoji
  • Publication number: 20100187678
    Abstract: In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a surface of a semiconductor assembly contacting to a polymer resin. In this manner, by the joint with the joint layer having the porous structure mainly made of Ag, thermal stress load of the Si chip can be reduced, and fatigue life of the joint layer itself can be improved. Besides, since adhesion of the polymer resin to the film can be enhanced by the anchor effect, occurrence of cracks in a bonding portion can be prevented, so that a highly-reliable Pb-free semiconductor device can be provided.
    Type: Application
    Filed: January 21, 2010
    Publication date: July 29, 2010
    Applicant: Renesas Technology Corp.
    Inventors: Ryoichi KAJIWARA, Shigehisa MOTOWAKI, Kazutoshi ITO, Toshiaki ISHII, Katsuo ARAI, Takuya NAKAJO, Hidemasa KAGII
  • Patent number: 7671462
    Abstract: A power semiconductor device, having a first semiconductor region, and a second semiconductor region; mounted with a first electrode pad on a semiconductor substrate main surface at the inside surrounded by the third semiconductor region, mounted in the second semiconductor region, and a multilayer substrate having first and second wiring layers, to take out an electrode of the semiconductor chip; joining the first wiring layer part for the first electrode, mounted on the multilayer substrate, in a region opposing to the semiconductor substrate main surface at the inside surrounded by the third semiconductor region, and the first electrode pad, by a conductive material; joining the first wiring layer part for the first electrode, and the second wiring layer at a conductive part; and extending the second wiring layer to the outside of a region opposing the semiconductor substrate main surface at the inside surrounded by the third semiconductor region.
    Type: Grant
    Filed: March 19, 2009
    Date of Patent: March 2, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Kozo Sakamoto, Toshiaki Ishii
  • Patent number: 7608917
    Abstract: A power semiconductor module and an inverter apparatus in which a device or a joining part is not mechanically damaged even when the temperature in use becomes a high temperature in the range of 175 to 250° C., resulting in excellent reliability at high temperature retaining test and thermal cycling test. Low thermal expansion ceramic substrates are disposed above and below the device. A material having a coefficient of thermal expansion of 10 ppm/K or less is disposed between the ceramic substrates. In addition, an inorganic material having a coefficient of thermal expansion in the range of 2 to 6 ppm/K or less is disposed around the device.
    Type: Grant
    Filed: May 16, 2007
    Date of Patent: October 27, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Ryoichi Kajiwara, Kazuhiro Suzuki, Toshiaki Ishii, Kazutoshi Itou
  • Publication number: 20090179321
    Abstract: A power semiconductor device, having a first semiconductor region, and a second semiconductor region; mounted with a first electrode pad on a semiconductor substrate main surface at the inside surrounded by the third semiconductor region, mounted in the second semiconductor region, and a multilayer substrate having first and second wiring layers, to take out an electrode of the semiconductor chip; joining the first wiring layer part for the first electrode, mounted on the multilayer substrate, in a region opposing to the semiconductor substrate main surface at the inside surrounded by the third semiconductor region, and the first electrode pad, by a conductive material; joining the first wiring layer part for the first electrode, and the second wiring layer at a conductive part; and extending the second wiring layer to the outside of a region opposing the semiconductor substrate main surface at the inside surrounded by the third semiconductor region.
    Type: Application
    Filed: March 19, 2009
    Publication date: July 16, 2009
    Inventors: Kozo Sakamoto, Toshiaki Ishii
  • Publication number: 20090160048
    Abstract: A semiconductor device includes a semiconductor chip and leads electrically connected to the electrodes of the semiconductor chip. A hollow radiator base houses the semiconductor device which is molded with high-thermal-conductivity resin having an electrical insulating property. The radiator base has a cooling-medium channel therein or radiating fins on the outside. Alternatively, the radiator base is housed in a second radiator base.
    Type: Application
    Filed: February 20, 2009
    Publication date: June 25, 2009
    Applicant: Hitachi, Ltd.
    Inventors: Kinya NAKATSU, Hideki MIYAZAKI, Yoshitaka TAKEZAWA, Toshiaki ISHII, Hiroshi HOZOJI
  • Patent number: 7514780
    Abstract: A power semiconductor device, having a first semiconductor region, and a second semiconductor region; mounted with a first electrode pad on a semiconductor substrate main surface at the inside surrounded by the third semiconductor region, mounted in the second semiconductor region, and a multilayer substrate having first and second wiring layers, to take out an electrode of the semiconductor chip; joining the first wiring layer part for the first electrode, mounted on the multilayer substrate, in a region opposing to the semiconductor substrate main surface at the inside surrounded by the third semiconductor region, and the first electrode pad, by a conductive material; joining the first wiring layer part for the first electrode, and the second wiring layer at a conductive part; and extending the second wiring layer to the outside of a region opposing the semiconductor substrate main surface at the inside surrounded by the third semiconductor region.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: April 7, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Kozo Sakamoto, Toshiaki Ishii
  • Patent number: 7504720
    Abstract: A semiconductor device includes a semiconductor chip and leads electrically connected to the electrodes of the semiconductor chip. A hollow radiator base houses the semiconductor device which is molded with high-thermal-conductivity resin having an electrical insulating property. The radiator base has a cooling-medium channel therein or radiating fins on the outside. Alternatively, the radiator base is housed in a second radiator base.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: March 17, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Kinya Nakatsu, Hideki Miyazaki, Yoshitaka Takezawa, Toshiaki Ishii, Hiroshi Hozoji
  • Publication number: 20080173398
    Abstract: A bonding material comprising metal particles coated with an organic substance having carbon atoms of 2 to 8, wherein the metal particles comprises first portion of 100 nm or less, and a second portion larger than 100 nm but not larger than 100 ?m, each of the portions having at least peak of a particle distribution, based on a volumetric base. The disclosure is further concerned with a bonding method using the bonding material.
    Type: Application
    Filed: December 27, 2007
    Publication date: July 24, 2008
    Inventors: Yusuke Yasuda, Toshiaki Morita, Eiichi Ide, Hiroshi Hozoji, Toshiaki Ishii
  • Publication number: 20080156398
    Abstract: It is an object of this invention to provide a bonding material capable of realizing bonding by metallic bonding at a bonding interface at a lower temperature compared to a bonding material using a metal particle having an average particle diameter of not more than 100 nm and a bonding method. There is provided a bonding material including a metal particle precursor being at least one selected from the group consisting of a particle of a metal oxide, a particle of a metal carbonate, and a particle of a metal carboxylate and having an average particle diameter of 1 nm to 50 ?m and a reducing agent composed of an organic substance, wherein the content of the metal particle precursor is more than 50 parts by mass and not more than 99 parts by mass per 100 parts by mass of the bonding material.
    Type: Application
    Filed: December 28, 2007
    Publication date: July 3, 2008
    Inventors: Yusuke Yasuda, Toshiaki Morita, Eiichi Ide, Hiroshi Hozoji, Toshiaki Ishii
  • Publication number: 20070298244
    Abstract: An object of the present invention is to provide a bonding material that is excellent in shear strength and a capability of heat radiation of a bonding layer and can be formed into a sheet. The present invention has a feature of providing a bonding material comprising metal fibers each of which is coated on its surface with an organic material or a metal oxide, has an aspect ratio not more than 2, and has a longitudinal length equal to or less than 100 ?m; and metal particles each of which is coated on its surface with an organic material or a metal oxide, has an aspect ratio equal to or less than 1.5, and has a particle size equal to or less than 100 nm, wherein sintering of the metal particles forms metallic bonds between the bonding material and surfaces of members to be bonded, thereby bonding the members to be bonded together.
    Type: Application
    Filed: June 21, 2007
    Publication date: December 27, 2007
    Inventors: YUSUKE YASUDA, Toshiaki Morita, Toshiaki Ishii
  • Publication number: 20070267739
    Abstract: A power semiconductor module and an inverter apparatus in which a device or a joining part is not mechanically damaged even when the temperature in use becomes a high temperature in the range of 175 to 250° C., resulting in excellent reliability at high temperature retaining test and thermal cycling test. Low thermal expansion ceramic substrates are disposed above and below the device. A material having a coefficient of thermal expansion of 10 ppm/K or less is disposed between the ceramic substrates. In addition, an inorganic material having a coefficient of thermal expansion in the range of 2 to 6 ppm/K or less is disposed around the device.
    Type: Application
    Filed: May 16, 2007
    Publication date: November 22, 2007
    Inventors: Ryoichi Kajiwara, Kazuhiro Suzuki, Toshiaki Ishii, Kazutoshi Itou
  • Patent number: 7298039
    Abstract: In order to provide a low-cost and high heat-radiating electronic circuit device featuring high compactness, little warpage, high air tightness, high moldability, high mass productivity, high reliability against thermal shocks, and high oil-proof reliability, a module structure made by packing a whole multi-layer circuit board which connects a semiconductor operating element, semiconductor memory elements, and passive elements thereon and part of a supporting material on which said multi-layer circuit board is placed into a single package by transfer-molding; wherein said multi-layer circuit board and said supporting material are bonded together with a compound metallic material made up from copper oxide and at least one metal selected from a set of gold, silver, and copper.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: November 20, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Nobutake Tsuyuno, Toshiaki Ishii, Toshiya Satoh, Mitsuhiro Masuda
  • Publication number: 20070215903
    Abstract: A power semiconductor device, having a first semiconductor region, and a second semiconductor region; mounted with a first electrode pad on a semiconductor substrate main surface at the inside surrounded by the third semiconductor region, mounted in the second semiconductor region, and a multilayer substrate having first and second wiring layers, to take out an electrode of the semiconductor chip; joining the first wiring layer part for the first electrode, mounted on the multilayer substrate, in a region opposing to the semiconductor substrate main surface at the inside surrounded by the third semiconductor region, and the first electrode pad, by a conductive material; joining the first wiring layer part for the first electrode, and the second wiring layer at a conductive part; and extending the second wiring layer to the outside of a region opposing the semiconductor substrate main surface at the inside surrounded by the third semiconductor region.
    Type: Application
    Filed: March 14, 2007
    Publication date: September 20, 2007
    Inventors: Kozo Sakamoto, Toshiaki Ishii
  • Patent number: 7217992
    Abstract: Semiconductor devices,-semiconductor wafers, and semiconductor modules are provided: wherein the semiconductor device has a small warp; damages at chip edge and cracks in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility. The semiconductor device 17 comprising: a semiconductor chip 64; a porous stress relaxing layer 3 provided on the plane, whereon circuits and electrodes are formed, of the semiconductor chip; a circuit layer 2 provided on the stress relaxing layer and connected to the electrodes; and external terminals 10 provided on the circuit layer; wherein an organic protecting film 7 is formed on the plane, opposite to the stress relaxing layer, of the semiconductor chip, and respective side planes of the stress relaxing layer, the semiconductor chip 6, and the protecting film 7 are exposed outside on a same plane.
    Type: Grant
    Filed: June 7, 2004
    Date of Patent: May 15, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Masahiko Ogino, Takumi Ueno, Shuji Eguchi, Akira Nagai, Toshiya Satoh, Toshiaki Ishii, Hiroyoshi Kokaku, Tadanori Segawa, Nobutake Tsuyuno, Asao Nishimura, Ichiro Anjoh
  • Publication number: 20070096278
    Abstract: A semiconductor device includes a semiconductor chip and leads electrically connected to the electrodes of the semiconductor chip. A hollow radiator base houses the semiconductor device which is molded with high-thermal-conductivity resin having an electrical insulating property. The radiator base has a cooling-medium channel therein or radiating fins on the outside. Alternatively, the radiator base is housed in a second radiator base.
    Type: Application
    Filed: August 17, 2006
    Publication date: May 3, 2007
    Applicant: Hitachi, Ltd.
    Inventors: Kinya Nakatsu, Hideki Miyazaki, Yoshitaka Takezawa, Toshiaki Ishii, Hiroshi Hozoji