Patents by Inventor Toshiaki Ishii

Toshiaki Ishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7165898
    Abstract: An optical module for an optical device and an optical fiber is constituted by a pre-molded plastic package. In forming the plastic package, the main flowing direction of the molding resin is substantially parallel with the optical axis of the optical fiber. The optical module is formed by molding the resin by injection using pressure and then solidifying the resin. When the plastic package is formed by comprehensive molding, the flowing direction of the resin is parallel with the optical axis direction of the optical fiber to be installed in the optical module. As a result, for comprehensive molding, the molding pressure applied to the optical fiber is reduced. By using the resin case that is formed, the resulting package exhibits high rigidity and low thermal expansion properties in connection with the flowing direction of the resin, thus reducing the external stress and thermal stress applied to the optical fiber.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: January 23, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Takeshil Kato, Koji Yoshida, Toshinori Hirataka, Toshiaki Ishii, Kazuyuki Fukuda, Tadaaki Ishikawa, Toshimasa Miura, Tsutomu Kono, Kimio Tatsuno
  • Patent number: 7038325
    Abstract: In a semiconductor device having a three-layered buffer layer comprising core layer 1 having interconnected foams such as a three-dimensional reticular structure and adhesive layers 2 provided on both sides of the core layer as a stress buffer layer between semiconductor chip 5 and wiring 4 to lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of the core layer 1 to total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: May 2, 2006
    Assignees: Hitachi Cable, Ltd., Renesas Technology Corp.
    Inventors: Masahiko Ogino, Shuji Eguchi, Akira Nagai, Takumi Ueno, Masanori Segawa, Hiroyoshi Kokaku, Toshiaki Ishii, Ichiro Anjoh, Asao Nishimura, Chuichi Miyazaki, Mamoru Mita, Norio Okabe
  • Patent number: 6888230
    Abstract: Semiconductor devices, semiconductor wafers, and semiconductor modules are provided, wherein: the semiconductor device has a small warp; damage at the chip edge and cracks occurring in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility. The semiconductor includes a semiconductor chip 64; a porous stress relaxing layer 3 provided on the plane, whereon circuits and electrodes are formed, of the semiconductor chip; a circuit layer 2 provided on the stress relaxing layer and connected to the electrodes; and external terminals 10 provided on the circuit layer; wherein an organic protecting film 7 is formed on the plane, opposite to the stress relaxing layer, of the semiconductor chip, and respective side planes of the stress relaxing layer, the semiconductor chip 6, and the protecting film 7 are exposed outside on the same plane.
    Type: Grant
    Filed: October 28, 1999
    Date of Patent: May 3, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Masahiko Ogino, Takumi Ueno, Shuji Eguchi, Akira Nagai, Toshiya Satoh, Toshiaki Ishii, Hiroyoshi Kokaku, Tadanori Segawa, Nobutake Tsuyuno, Asao Nishimura, Ichiro Anjoh
  • Patent number: 6878448
    Abstract: The present invention provides a biphenyl based epoxy resin comprising a curing agent and an inorganic filler containing an alkali alkaline earth metal oxide wherein the epoxy resin has a variation rate of hardness at 25° C. and a relative humidity of 50% for 72 hours of less than 10% and a variation rate of flow at 25° C. and a relative humidity of 20% or below for 72 hours of less than 20%.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: April 12, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Toshiaki Ishii, Hiroyoshi Kokaku, Akira Nagai, Takao Miwa
  • Publication number: 20050030823
    Abstract: In order to provide a low-cost and high heat-radiating electronic circuit device featuring high compactness, little warpage, high air tightness, high moldability, high mass productivity, high reliability against thermal shocks, and high oil-proof reliability, a module structure made by packing a whole multi-layer circuit board which connects a semiconductor operating element, semiconductor memory elements, and passive elements thereon and part of a supporting material on which said multi-layer circuit board is placed into a single package by transfer-molding; wherein said multi-layer circuit board and said supporting material are bonded together with a compound metallic material made up from copper oxide and at least one metal selected from a set of gold, silver, and copper.
    Type: Application
    Filed: August 4, 2004
    Publication date: February 10, 2005
    Inventors: Nobutake Tsuyuno, Toshiaki Ishii, Toshiya Satoh, Mitsuhiro Masuda
  • Publication number: 20040217453
    Abstract: Semiconductor devices,-semiconductor wafers, and semiconductor modules are provided: wherein the semiconductor device has a small warp; damages at chip edge and cracks in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility.
    Type: Application
    Filed: June 7, 2004
    Publication date: November 4, 2004
    Inventors: Masahiko Ogino, Takumi Ueno, Shuji Eguchi, Akira Nagai, Toshiya Satoh, Toshiaki Ishii, Hiroyoshi Kokaku, Tadanori Segawa, Nobutake Tsuyuno, Asao Nishimura, Ichiro Anjoh
  • Publication number: 20040212965
    Abstract: A resin-sealed electronic circuit apparatus capable of maintaining a high heat-dissipating property and packaging density in applications where high hermetic-sealing property and durability are required. The electronic circuit apparatus comprises at least two wiring circuit boards 12 and 13 on which electronic components are mounted. The wiring circuit boards 12 and 13 are fixed to a heat sink 14 having a high heat conductivity via an adhesive 9 and 10. The entirety of the wiring circuit boards 12 and 13 and heat sink 14, as well as a part of an external connection terminal 8 are hermetically sealed and integrally molded by a thermosetting resin composition 7. The electronic circuit apparatus is small and highly reliable and can be provided at low cost.
    Type: Application
    Filed: March 17, 2004
    Publication date: October 28, 2004
    Inventors: Toshiaki Ishii, Nobutake Tsuyuno, Mitsuhiro Masuda, Noriyoshi Urushiwara, Akira Matsushita
  • Publication number: 20040195702
    Abstract: In a semiconductor device having a three-layered buffer layer comprising core layer 1 having interconnected foams such as a three-dimensional reticular structure and adhesive layers 2 provided on both sides of the core layer as a stress buffer layer between semiconductor chip 5 and wiring 4 to lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of the core layer 1 to total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.
    Type: Application
    Filed: April 23, 2004
    Publication date: October 7, 2004
    Inventors: Masahiko Ogino, Shuji Eguchi, Akira Nagai, Takumi Ueno, Masanori Segawa, Hiroyoshi Kokaku, Toshiaki Ishii, Ichiro Anjoh, Asao Nishimura, Chuichi Miyazaki, Mamoru Mita, Norio Okabe
  • Patent number: 6791182
    Abstract: At least a part of the inner leads 1a of a lead frame 1 is covered with a plating for a metallic fine wire connection, at least the entire portion where the lead frame 1 joins with the adhesive layer 2 is covered by at least one metal or alloy thereof different from the metallic fine wire connecting use plating. The metal or alloy is selected from the group consisting of gold, platinum, iridium, rhodium, palladium, ruthenium, indium, tin, molybdenum, tungsten, gallium, zinc, chromium, niobium, tantalum, titanium and zirconium. Thereby, generation of defects, such as leakage and shorting, due to ion migration can be prevented.
    Type: Grant
    Filed: March 25, 2002
    Date of Patent: September 14, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Junpei Kusukawa, Ryozo Takeuchi, Toshiaki Ishii, Hiromichi Suzuki, Fujio Ito, Takafumi Nishita, Akihiko Kameoka, Masaru Yamada
  • Publication number: 20040165840
    Abstract: The present invention is to reduce the package cost and secure the high reliability in an optical module having an optical device and an optical fiber.
    Type: Application
    Filed: February 27, 2004
    Publication date: August 26, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Takeshi Kato, Koji Yoshida, Toshinori Hirataka, Toshiaki Ishii, Kazuyuki Fukuda, Tadaaki Ishikawa, Toshimasa Miura, Tsutomu Kono, Kimio Tatsuno
  • Patent number: 6726375
    Abstract: An optical module for an optical device and an optical fiber is constituted by a pre-molded plastic package. In forming the plastic package, the main flowing direction of the molding resin is substantially parallel with the optical axis of the optical fiber. The optical module is formed by molding the resin by injection using pressure and then solidifying the resin. When the plastic package is formed by comprehensive molding, the flowing direction of the resin is parallel with the optical axis direction of the optical fiber to be installed in the optical module. As a result, for comprehensive molding, the molding pressure applied to the optical fiber is reduced. By using the resin case that is formed, the resulting package exhibits high rigidity and low thermal expansion properties in connection with the flowing direction of the resin, thus reducing the external stress and thermal stress applied to the optical fiber.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: April 27, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Takeshil Kato, Koji Yoshida, Toshinori Hirataka, Toshiaki Ishii, Kazuyuki Fukuda, Tadaaki Ishikawa, Toshimasa Miura, Tsutomu Kono, Kimio Tatsuno
  • Publication number: 20030052420
    Abstract: Described is a semiconductor device comprising a plurality of inner leads each made of copper or an alloy thereof; a heat sink made of copper or an alloy thereof, bonded to one end of each of a plurality of inner leads via an insulating adhesive layer and having a semiconductor element mounted on the heat sink via a metal wire; a plurality of metal wires each electrically connecting the semiconductor element and each of the plurality of inner leads; an encapsulating resin encapsulating the semiconductor element and the plurality of metal wires; and a plurality of outer leads protruded outside of the encapsulating resin and bent in the gullwing form. The encapsulating resin has been added with an additive forming a compound with an ionic impurity so that water at the peeling portion becomes near neutral, which prevents reaction and easy elution of copper, thereby preventing Cu migration.
    Type: Application
    Filed: August 22, 2002
    Publication date: March 20, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Hiromichi Suzuki, Akihiko Kameoka, Masaru Yamada, Takafumi Nishita, Fujio Ito, Junpei Kusukawa, Ryozo Takeuchi, Toshiaki Ishii
  • Publication number: 20030042597
    Abstract: In a semiconductor device which is assembled by making use of a lead frame 1 with a heat radiation plate 3 in which the lead frame 1 and the heat radiation plate 3 made of copper or copper alloy are joined by an adhesive layer 2 formed on a surface of the heat radiation plate 3 and at least a part of the inner leads 1a of the lead frame 1 is applied of a plating for a metallic fine wire connection, at least the entire portion where the lead frame 1 joins with the adhesive layer 2 is covered by at least one metal or alloy thereof different from the metallic fine wire connecting use plating selected from the group consisting of gold, platinum, iridium, rhodium, palladium, ruthenium, indium, tin, molybdenum, tungsten, gallium, zinc, chromium, niobium, tantalum, titanium and zirconium. Thereby, generation of inconveniences such as leakage and shorting due to ion migration can be prevented.
    Type: Application
    Filed: March 25, 2002
    Publication date: March 6, 2003
    Inventors: Junpei Kusukawa, Ryozo Takeuchi, Toshiaki Ishii, Hiromichi Suzuki, Fujio Ito, Takafumi Nishita, Akihiko Kameoka, Masaru Yamada
  • Publication number: 20020197026
    Abstract: The present invention is to reduce the package cost and secure the high reliability in an optical module having an optical device and an optical fiber.
    Type: Application
    Filed: August 16, 2002
    Publication date: December 26, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Takeshil Kato, Koji Yoshida, Toshinori Hirataka, Toshiaki Ishii, Kazuyuki Fukuda, Tadaaki Ishikawa, Toshimasa Miura, Tsutomu Kono, Kimio Tatsuno
  • Publication number: 20020158343
    Abstract: In a semiconductor device having a three-layered buffer layer comprising core layer 1 having interconnected foams such as a three-dimensional reticular structure and adhesive layers 2 proved on both sides of the core layer as a stress buffer layer between semiconductor chip 5 and wiring 4 to lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of core layer 1 to total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.
    Type: Application
    Filed: April 30, 2002
    Publication date: October 31, 2002
    Inventors: Masahiko Ogino, Shuji Eguchi, Akira Nagai, Takumi Ueno, Masanori Segawa, Hiroyoshi Kokaku, Toshiaki Ishii, Ichiro Anjoh, Asao Nishimura, Chuichi Miyazaki, Mamoru Mita, Norio Okabe
  • Patent number: 6457877
    Abstract: An optical module for an optical device and an optical fiber is constituted by a pre-molded plastic package. In forming the plastic package, the main flowing direction of the molding resin is substantially parallel with the optical axis of the optical fiber. The optical module is formed by molding the resin by an injection method using pressure and then solidifying the resin. When the plastic package is formed by comprehensive molding, the flowing direction of the resin is parallel with the optical axis direction of the optical fiber to be installed in the optical module. As a result, for comprehensive molding, the molding pressure applied to the optical fiber is reduced. By using the resin case that is formed, the resulting package exhibits high rigidity and low thermal expansion properties in connection with the flowing direction of the resin, thus reducing the external stress and thermal stress applied to the optical fiber.
    Type: Grant
    Filed: February 21, 2001
    Date of Patent: October 1, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Takeshil Kato, Koji Yoshida, Toshinori Hirataka, Toshiaki Ishii, Kazuyuki Fukuda, Tadaaki Ishikawa, Toshimasa Miura, Tsutomu Kono, Kimio Tatsuno
  • Patent number: 6433440
    Abstract: In a semiconductor device having a three-layered buffer layer comprising core layer 1 having interconnected foams such as a three-dimensional reticular structure and adhesive layers 2 provided on both sides of the core layer as a stress buffer layer between semiconductor chip 5 and wiring 4 to lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of core layer 1 to total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: August 13, 2002
    Assignees: Hitachi, Ltd., Hitachi Cable, Ltd.
    Inventors: Masahiko Ogino, Shuji Eguchi, Akira Nagai, Takumi Ueno, Masanori Segawa, Hiroyoshi Kokaku, Toshiaki Ishii, Ichiro Anjoh, Asao Nishimura, Chuichi Miyazaki, Mamoru Mita, Norio Okabe
  • Patent number: 6423571
    Abstract: A method of forming a semiconductor device having a multi-layered wiring structure that includes a conductor layer to be electrically connected to a packaging substrate, with the multi-layered wiring structure being provided on a circuit formation surface of a semiconductor chip. Ball-like terminals are formed, disposed in a grid array on the surface of the multi-layered wiring structure on the packaging substrate side. The multi-layered wiring structure is formed to include a buffer layer for relieving a thermal stress provided between the semiconductor chip and the packaging substrate, due to the packaging procedure. In the semiconductor device formed, the wiring distance is shorter than that of a conventional semiconductor device, so that an inductance component becomes smaller, to thereby increase signal speed.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: July 23, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Masahiko Ogino, Akira Nagai, Shuji Eguchi, Toshiaki Ishii, Masanori Segawa, Haruo Akahoshi, Akio Takahashi, Takao Miwa, Naotaka Tanaka, Ichirou Anjou
  • Publication number: 20010051393
    Abstract: A method of forming a semiconductor device having a multi-layered wiring structure that includes a conductor layer to be electrically connected to a packaging substrate, with the multi-layered wiring structure being provided on a circuit formation surface of a semiconductor chip. Ball-like terminals are formed, disposed in a grid array on the surface of the multi-layered wiring structure on the packaging substrate side. The multi-layered wiring structure is formed to include a buffer layer for relieving a thermal stress provided between the semiconductor chip and the packaging substrate, due to the packaging procedure. In the semiconductor device formed, the wiring distance is shorter than that of a conventional semiconductor device, so that an inductance component becomes smaller, to thereby increase signal speed.
    Type: Application
    Filed: June 20, 2001
    Publication date: December 13, 2001
    Inventors: Masahiko Ogino, Akira Nagai, Shuji Eguchi, Toshiaki Ishii, Masanori Segawa, Haruo Akahoshi, Akio Takahashi, Takao Miwa, Naotaka Tanaka, Ichirou Anjou
  • Patent number: 6282352
    Abstract: An optical module for an optical device and an optical fiber is constituted by a pre-molded plastic package. In forming the plastic package, the main flowing direction of the molding resin is substantially parallel with the optical axis of the optical fiber. The optical module is formed by molding the resin by an injection method using pressure and then solidifying the resin. When the plastic package is formed by comprehensive molding, the flowing direction of the resin is parallel with the optical axis direction of the optical fiber to be installed in the optical module. As a result, for comprehensive molding, the molding pressure applied to the optical fiber is reduced. By using the resin case that is formed, the resulting package exhibits high rigidity and low thermal expansion properties in connection with the flowing direction of the resin, thus reducing the external stress and thermal stress applied to the optical fiber.
    Type: Grant
    Filed: January 7, 2000
    Date of Patent: August 28, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Takeshi Kato, Koji Yoshida, Toshinori Hirataka, Toshiaki Ishii, Kazuyuki Fukuda, Tadaaki Ishikawa, Toshimasa Miura, Tsutomu Kono, Kimio Tatsuno