Abstract: The present disclosure relates to integrated circuits, and more particularly, to a method for identifying unprogrammed bits for one-time-programmable memory (OTPM) and a corresponding structure. In particular, the present disclosure relates to a structure including: a read circuit configured to perform at least one read operation at an address for a twin-cell one-time-programmable-memory (OTPM); and a comparison circuit configured to identify whether at least one bit of the address for the twin-cell OTPM has been programmed based on the at least one read operation.

Abstract: The present disclosure relates to integrated circuits, and more particularly, to a method for identifying unprogrammed bits for one-time-programmable memory (OTPM) and a corresponding structure. In particular, the present disclosure relates to a structure including: a read circuit configured to perform at least one read operation at an address for a twin-cell one-time-programmable-memory (OTPM); and a comparison circuit configured to identify whether at least one bit of the address for the twin-cell OTPM has been programmed based on the at least one read operation.

Abstract: The present disclosure relates to integrated circuits, and more particularly, to a method for identifying unprogrammed bits for one-time-programmable memory (OTPM) and a corresponding structure. In particular, the present disclosure relates to a structure including: a read circuit configured to perform at least one read operation at an address for a twin-cell one-time-programmable-memory (OTPM); and a comparison circuit configured to identify whether at least one bit of the address for the twin-cell OTPM has been programmed based on the at least one read operation.

Abstract: Disclosed is a memory structure including an array of memory cells and a read circuit. The read circuit includes two registers configured to capture and store two different digital-to-analog converter (DAC) codes, which correspond to two different reference currents that approximate two different output currents generated on a bitline during consecutive single-ended current sensing processes directed to the same selected memory cell but using different input voltages. Optionally, the read circuit can also include a current-voltage (I-V) slope calculator, which uses the two different DAC codes to calculate an I-V slope characteristic of the selected memory cell, and a bit generator, which performs a comparison of the I-V slope characteristic and a reference I-V slope characteristic and based on results of the comparison, generates and outputs a bit with a logic value that represents the data storage state of the selected memory cell. Also disclosed is an associated method.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to charge trap memory devices and methods of manufacture and operation. The semiconductor memory includes: a charge trap transistor comprising a gate structure, a source region and a drain region; and a self-heating circuit which selectively applies an alternating bias direction between the source region and the drain region of the charge trap transistor to provide an erase operation or a programming operation of the charge trap transistor.

Abstract: A Physically Unclonable Function (PUF) structure includes an array of twin cells divided into two portions: one with first columns and one with second columns. Cells in each first column are connected to a corresponding pair of first bitlines. Cells in each second column are connected to a corresponding pair of second bitlines. A first column decoder is connected to the first bitlines and to a first input of sense amplifier (SA) and a second column decoder is connected to the second bitlines and to a second input of SA. Each read operation to generate a bit is directed to a first cell in a first column and a second cell in a second column and, during the read operation, signals on only one first bitline of the first column containing the first cell and only one second bitline of the second column containing the second cell are compared.

Abstract: Embodiments of the present invention provide an authenticating service of a chip having an intrinsic identifier (ID). In a typical embodiment, an authenticating device is provided that includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to charge trap memory devices and methods of manufacture and operation. The semiconductor memory includes: a charge trap transistor comprising a gate structure, a source region and a drain region; and a self-heating circuit which selectively applies an alternating bias direction between the source region and the drain region of the charge trap transistor to provide an erase operation or a programming operation of the charge trap transistor.

Abstract: The present disclosure relates to a data dependent sense amplifier with symmetric margining. In particular, the present disclosure relates to a structure including a bias generator circuit that is configured to provide symmetric margining between two logic states of a memory circuit.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to program and erase memory structures and methods of manufacture. The semiconductor memory includes: a charge trap transistor; and a self-heating circuit which selectively applies voltages to terminals of the charge trap transistor to assist in erase operations of the charge trap transistor.

Abstract: Embodiments of the present invention provide an authenticating service of a chip having an intrinsic identifier (ID). In a typical embodiment, an authenticating device is provided that includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.

Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.

Abstract: Embodiments of the present invention provide an authenticating service of a chip having an intrinsic identifier (ID). In a typical embodiment, an authenticating device is provided that includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.

Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to program and erase memory structures and methods of manufacture. The semiconductor memory includes: a charge trap transistor; and a self-heating circuit which selectively applies voltages to terminals of the charge trap transistor to assist in erase operations of the charge trap transistor.

Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.

Abstract: Embodiments of the present invention provide an authenticating service of a chip having an intrinsic identifier (ID). In a typical embodiment, an authenticating device is provided that includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.

Abstract: An authenticating service of a chip having an intrinsic identifier (ID) is provided. The authenticating device includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.

Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.

Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.