Patents by Inventor Toshiaki Kirihata

Toshiaki Kirihata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Implementing precise resistance measurement for 2D array efuse bit cell using differential sense amplifier, balanced bitlines, and programmable reference resistor
    Patent number: 7764531
    Abstract: A method and circuit for implementing precise eFuse resistance measurement, and a design structure on which the subject circuit resides are provided. An eFuse sense amplifier coupled to an eFuse array and used for current measurements includes balanced odd and even bitlines, and a plurality of programmable reference resistors connected to the balanced odd and even bitlines. First a baseline current measurement is made through one of the programmable reference resistors, and used to identify a network baseline resistance. A current measurement is made for an eFuse path including a selected eFuse and used to identify the resistance of the selected eFuse.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: July 27, 2010
    Assignee: International Business Machines Corporation
    Inventors: Anthony Gus Aipperspach, Toshiaki Kirihata, Phil Christopher Felice Paone, Brian Joy Reed, John Matthew Safran, David Edward Schmitt, Gregory John Uhlmann
  • Implementing Precise Resistance Measurement for 2D Array Efuse Bit Cell Using Differential Sense Amplifier, Balanced Bitlines, and Programmable Reference Resistor
    Publication number: 20100067319
    Abstract: A method and circuit for implementing precise eFuse resistance measurement, and a design structure on which the subject circuit resides are provided. An eFuse sense amplifier coupled to an eFuse array and used for current measurements includes balanced odd and even bitlines, and a plurality of programmable reference resistors connected to the balanced odd and even bitlines. First a baseline current measurement is made through one of the programmable reference resistors, and used to identify a network baseline resistance. A current measurement is made for an eFuse path including a selected eFuse and used to identify the resistance of the selected eFuse.
    Type: Application
    Filed: September 18, 2008
    Publication date: March 18, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony Gus Aipperspach, Toshiaki Kirihata, Phil Christopher Felice Paone, Brian Joy Reed, John Matthew Safran, David Edward Schmitt, Gregory John Uhlmann
  • Design structure for improving sensing margin of electrically programmable fuses
    Patent number: 7609577
    Abstract: A design structure embodied in a machine readable medium used in a design process includes an apparatus for sensing the state of a programmable resistive memory element device, the apparatus further including a latch device coupled to a fuse node and a reference node, the fuse node included within a fuse leg and the reference node configured within a reference resistance leg, the latch device configured to detect a differential signal developed between the reference node and the fuse node as the result of sense current passed through the fuse leg and the reference resistance leg; and the fuse and reference resistance legs further configured for first and second sensing modes, wherein the second sensing mode utilizes a different level of current than the first sensing mode.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: October 27, 2009
    Assignee: International Business Machines Corporation
    Inventors: Darren L. Anand, Gregory J. Fredeman, Toshiaki Kirihata, Alan J. Leslie, John M. Safran
  • Method and Circuit for Implementing Efuse Resistance Screening
    Publication number: 20090212850
    Abstract: A method and circuit for implementing eFuse resistance screening, and a design structure on which the subject circuit resides are provided. An eFuse is sensed using a first reference resistor. Responsive to the eFuse being sensed as blown with the first reference resistor, the eFuse is sensed using a second reference resistor having a higher resistance than the first reference resistor. Responsive to the eFuse being sensed as unblown with the second reference resistor, the eFuse is recorded as poorly blown. Reliability concerns are identified quickly and accurately without being required to measure the resistance of the eFuse.
    Type: Application
    Filed: February 26, 2008
    Publication date: August 27, 2009
    Inventors: Anthony Gus Aipperspach, Toshiaki Kirihata, Phil Christopher Felice Paone, Brian Joy Reed, David Edward Schmitt, Gregory John Uhlmann
  • Method for improving sensing margin of electrically programmable fuses
    Patent number: 7525831
    Abstract: A method for determining the state of a programmable resistive memory element includes passing a first level of current through a fuse leg and a reference resistance leg of a test circuit including the programmable resistive memory element; detecting a differential signal developed between a reference node and a fuse node of the test circuit as a result of the first level of current; passing a second level of current through the fuse leg and the reference leg of a test circuit, the second level of current being higher than the first level of current so as to enable detection of trip resistance of the test circuit at a lower value than with respect to the first level of current; and detecting a differential signal developed between the reference node and the fuse node of the test circuit as a result of the second level of current.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: April 28, 2009
    Assignee: International Business Machines Corporation
    Inventors: Darren L. Anand, Gregory J. Fredeman, Toshiaki Kirihata, Alan J. Leslie, John M. Safran
  • Three Dimensional Twisted Bitline Architecture for Multi-port Memory
    Publication number: 20090103390
    Abstract: Embodiments of the present invention provide a memory array of dual part cells and design structure thereof. The memory array has a pair of twisted write bit lines and a pair of twisted read bit lines for each column. The twist is made by alternating the vertical position of each bit line pair in each section of a column, with the result of generating common mode nose and of reducing differential mode noise.
    Type: Application
    Filed: October 19, 2007
    Publication date: April 23, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hoki Kim, Toshiaki Kirihata
  • Random Access Electrically Programmable E-Fuse Rom
    Publication number: 20080316789
    Abstract: A one-time-programmable-read-only-memory (OTPROM) is implemented in a two-dimensional array of aggressively scaled suicide migratable e-fuses. Word line selection is performed by decoding logic operating at VDD while the bit line drive is switched between VDD and a higher voltage, Vp for programming. The OTPROM is thus compatible with and can be integrated with other technologies without a cost adder and supports optimization of the high current path for minimal voltage drop during fuse programming. A differential sense amplifier with a programmable reference is used for improved sense margins and can support an entire bit line rather than sense amplifiers being provided for individual fuses.
    Type: Application
    Filed: August 30, 2006
    Publication date: December 25, 2008
    Inventors: Gregory J. Fredeman, Toshiaki Kirihata, Alan J. Leslie, John M. Safran
  • FLEXIBLE ROW REDUNDANCY SYSTEM
    Publication number: 20080229144
    Abstract: A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; wherein the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.
    Type: Application
    Filed: June 2, 2008
    Publication date: September 18, 2008
    Applicant: International Business Machines Corporation
    Inventors: Louis L. Hsu, Gregory J. Fredeman, Rajiv V. Joshi, Toshiaki Kirihata
  • Flexible row redundancy system
    Patent number: 7404113
    Abstract: A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.
    Type: Grant
    Filed: January 7, 2005
    Date of Patent: July 22, 2008
    Assignee: International Business Machines Corporation
    Inventors: Louis L. Hsu, Gregory J. Fredeman, Rajiv V. Joshi, Toshiaki Kirihata
  • DESIGN STRUCTURE FOR IMPROVING SENSING MARGIN OF ELECTRICALLY PROGRAMMABLE FUSES
    Publication number: 20080030260
    Abstract: A design structure embodied in a machine readable medium used in a design process includes an apparatus for sensing the state of a programmable resistive memory element device, the apparatus further including a latch device coupled to a fuse node and a reference node, the fuse node included within a fuse leg and the reference node configured within a reference resistance leg, the latch device configured to detect a differential signal developed between the reference node and the fuse node as the result of sense current passed through the fuse leg and the reference resistance leg; and the fuse and reference resistance legs further configured for first and second sensing modes, wherein the second sensing mode utilizes a different level of current than the first sensing mode.
    Type: Application
    Filed: October 15, 2007
    Publication date: February 7, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Darren Anand, Gregory Fredeman, Toshiaki Kirihata, Alan Leslie, John Safran
  • METHOD FOR IMPROVING SENSING MARGIN OF ELECTRICALLY PROGRAMMABLE FUSES
    Publication number: 20080025071
    Abstract: A method for determining the state of a programmable resistive memory element includes passing a first level of current through a fuse leg and a reference resistance leg of a test circuit including the programmable resistive memory element; detecting a differential signal developed between a reference node and a fuse node of the test circuit as a result of the first level of current; passing a second level of current through the fuse leg and the reference leg of a test circuit, the second level of current being higher than the first level of current so as to enable detection of trip resistance of the test circuit at a lower value than with respect to the first level of current; and detecting a differential signal developed between the reference node and the fuse node of the test circuit as a result of the second level of current.
    Type: Application
    Filed: October 5, 2007
    Publication date: January 31, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Darren Anand, Gregory Fredeman, Toshiaki Kirihata, Alan Leslie, John Safran
  • Apparatus and method for improving sensing margin of electrically programmable fuses
    Patent number: 7307911
    Abstract: An apparatus for sensing the state of a programmable resistive memory element device includes a latch device is coupled to a fuse node and a reference node, the fuse node included within a fuse leg and the reference node configured within a reference resistance leg. The latch device is configured to detect a differential signal developed between the reference node and the fuse node as the result of sense current passed through the fuse leg and the reference resistance leg. The fuse and reference resistance legs are further configured for first and second sensing modes, wherein the second sensing mode utilizes a different level of current than the first sensing mode.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: December 11, 2007
    Assignee: International Business Machines Corporation
    Inventors: Darren L. Anand, Gregory J. Fredeman, Toshiaki Kirihata, Alan J. Leslie, John M. Safran
  • Three dimensional twisted bitline architecture for multi-port memory
    Patent number: 7286437
    Abstract: A memory array of dual part cells has a pair of twisted write bitlines and a pair of twisted read bitlines for each column. The twist is made by alternating the vertical position of each bitline pair in each section of a column, with the result of generating common mode nose and of reducing differential mode noise.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: October 23, 2007
    Assignee: International Business Machines Corporation
    Inventors: Hoki Kim, Toshiaki Kirihata
  • Command multiplier for built-in-self-test
    Patent number: 7194670
    Abstract: Disclosed is a flexible command multiplication scheme for the built-in-self test (BIST) of a high-speed embedded memory array that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A stand-alone BIST logic controller operates at a lower frequency and communicates with a command multiplier using a low-speed BIST instruction seed set. The command multiplier uses offset or directive registers to drive a logic unit or ALU to generate “n” sets of CAD information which are then time-multiplexed to the embedded memory at a speed “n” times faster than the BIST operating speed.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: March 20, 2007
    Assignee: International Business Machines Corp.
    Inventors: Jonathan R. Fales, Gregory J. Fredeman, Kevin W. Gorman, Mark D. Jacunski, Toshiaki Kirihata, Alan D. Norris, Paul C. Parries, Matthew R. Wordeman
  • Three Dimensional Twisted Bitline Architecture for Multi-Port Memory
    Publication number: 20060285420
    Abstract: A memory array of dual part cells has a pair of twisted write bitlines and a pair of twisted read bitlines for each column. The twist is made by alternating the vertical position of each bitline pair in each section of a column, with the result of generating common mode nose and of reducing differential mode noise.
    Type: Application
    Filed: June 17, 2005
    Publication date: December 21, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hoki Kim, Toshiaki Kirihata
  • SINGLE CYCLE REFRESH OF MULTI-PORT DYNAMIC RANDOM ACCESS MEMORY (DRAM)
    Publication number: 20060285411
    Abstract: A multi-port DRAM having refresh cycles interleaved with normal read and write operations implements a single cycle refresh sequence by deferring the write portion of the sequence until the next refresh cycle. During a single clock cycle, the system writes stored data from a refresh buffer into a row in the memory array and then reads data from one row of the memory array into the buffer.
    Type: Application
    Filed: June 16, 2005
    Publication date: December 21, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hoki Kim, Toshiaki Kirihata
  • Single cycle refresh of multi-port dynamic random access memory (DRAM)
    Patent number: 7145829
    Abstract: A multi-port DRAM having refresh cycles interleaved with normal read and write operations implements a single cycle refresh sequence by deferring the write portion of the sequence until the next refresh cycle. During a single clock cycle, the system writes stored data from a refresh buffer into a row in the memory array and then reads data from one row of the memory array into the buffer.
    Type: Grant
    Filed: June 16, 2005
    Date of Patent: December 5, 2006
    Assignee: International Business Machines Corporation
    Inventors: Hoki Kim, Toshiaki Kirihata
  • System and method for variable array architecture for memories
    Patent number: 7146471
    Abstract: A memory system that employs simultaneous activation of at least two dissimilar memory arrays, during a data manipulation, such as read or write operations is disclosed. An exemplary embodiment includes a memory system containing a plurality of arrays, each in communication with a common controller, wherein the arrays are activated by different supply voltage (Vdd). When a processor sends a command to retrieve or write data to the memory system, two or more arrays are addressed to supply the required data. By proper partitioning of the data between dissimilar arrays, the efficiency of data reading is improved.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: December 5, 2006
    Assignees: International Business Machines Corp., Infineon Technologies AG
    Inventors: Toshiaki Kirihata, Gerhard Mueller, Wing K. Luk
  • Flexible row redundancy system
    Patent number: 7093171
    Abstract: A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.
    Type: Grant
    Filed: April 3, 2002
    Date of Patent: August 15, 2006
    Assignee: International Business Machines Corporation
    Inventors: Louis L. Hsu, Gregory J. Fredeman, Rajiv V. Joshi, Toshiaki Kirihata
  • Method and structure for enabling a redundancy allocation during a multi-bank operation
    Patent number: 7085180
    Abstract: A method for allocating redundancies during a multi-bank operation in a memory device which includes two or more redundancy domains is described. The method includes steps of enabling a pass/fail bit detection to activate a given bank. The pass/fail bit detection is prompted only for a selected domain and is disabled when it addresses other domains. By altering the domain selection, it is possible to enable a redundancy allocation for any domain regardless of the multi-bank operation. The method may preferably be realized by using a dynamic exclusive-OR logic with true and complement expected data pairs. When combined with simple pointer logic, the selection of domains may be generated internally, simplifying the built in self-test and other test control protocols, while at the same time tracking those that fail.
    Type: Grant
    Filed: February 12, 2004
    Date of Patent: August 1, 2006
    Assignee: International Business Machines Corporation
    Inventors: Gregory J. Fredeman, Mark D. Jacunski, Toshiaki Kirihata, Matthew R. Wordeman