Abstract: In a digital information system for realizing the sale of information or the like having a commercial value in the form of a digital signal, and an audio processor, and signal processor suitably used with the system, when a digital signal is received/delivered, a digital signal source is connected directly to a player for receiving and storing a specified information, which is reproduced by the player independently. A voice interval of a digital audio signal is processed to realize the slow and fast playback. The system includes a data compressor and a data extender of simple configuration. The value of the digital signal received/delivered can be exhibited directly. A selling system is constructed easily, and the player is simple in configuration and easy to operate by anyone.

Abstract: In a digital information system for realizing the sale of information or the like having a commercial value in the form of a digital signal, and an audio processor, and signal processor suitably used with the system, when a digital signal is received/delivered, a digital signal source is connected directly to a player for receiving and storing a specified information, which is reproduced by the player independently. A voice interval of a digital audio signal is processed to realize the slow and fast playback. The system includes a data compressor and a data extender of simple configuration. The value of the digital signal received/delivered can be exhibited directly. A selling system is constructed easily, and the player is simple in configuration and easy to operate by anyone.

Abstract: There is provided a customized personal terminal device capable of operating in response to input data peculiar to the operator, comprising a speech recognition unit for recognizing inputted speech, an image recognition unit for recognizing inputted image, and an instruction recognition unit for recognizing an inputted instruction. Neural networks respectively provided in at least two of the speech, image and instruction recognition units, a bus operatively connected to the respective recognition units, a processor operatively connected to the bus to perform processing upon the speech, and image and instruction recognized by the recognition units. Also, memory is operatively connected to the bus, and a control unit exercises control over information exchange between respective recognition units and the memory under the control of the processor.

Abstract: A semiconductor light-emitting device includes a plurality of semiconductor rods, each of which has a pn junction. The semiconductor rods are formed on a semiconductor substrate such that the plurality of semiconductor rods are arranged at a distance substantially equal to an integer multiple of the wavelength of light emitted from the semiconductor rod. With such devices, various novel optical devices such as a micro-cavity laser of which the threshold current is extremely small and a coherent light-emitting device having no threshold value can be realized.

Abstract: A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

Abstract: A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

Abstract: A static RAM memory is divided into a plurality of mats (12). Word lines (16) in each pair of mats are accessed by an x-decoder (14). Columns or bit lines are accessed by a y-decoder (20) which selectively connect pairs of bit lines (22) to common data bus segments (24). Transistors (60, 62) connect selected bit lines with a load during a write cycle to stabilize those bit lines and memory cells into which data is written. The x-decoders are connected with near word lines (16a) for addressing a near half of each mat and are operatively connected with remote word lines (16b) for addressing word lines in a remote half of each mat. In this manner, each mat is divided into two effective mats. The bit lines of all the effective mats within an actual mat are connected with the same output data bus segment. A pair of sensing amplifiers (32) is provided for each bit of memory which is accessed concurrently, e.g. eight bits, such that the high and low output of each flip-flop memory cell (18) are both amplified.

Abstract: There is provided a customized personal terminal device capable of operating in response to input data peculiar to the operator, comprising a speech recognition unit for recognizing inputted speech, an image recognition unit for recognizing inputted image, and an instruction recognition unit for recognizing an inputted instruction. Neural networks are provided in at least two of the speech, image and instruction recognition units, a bus operatively connected to the respective recognition units, a processor operatively connected to the bus to perform processing upon the speech, and image and instruction recognized by the recognition units. Also, memory is operatively connected to the bus, and a control unit exercises control over information exchange between respective recognition units and the memory under the control of the processor.

Abstract: A semiconductor static random access memory having a high .alpha.-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor.

Abstract: Electric charge is supplied to a circuit node being in a charge storing state within a signal processor in response to a signal-processing commencing signal. The processor is operated in a low-temperature range, for example, in the range of temperature below 200K. By this structure, a leakage current is reduced, a high degree of integration equivalent to that of a dynamic circuit can be obtained, and the simplicity of a static circuit not requiring any complicated internal/external timing signals can be realized. Also disclosed is a semiconductor device, and method of forming such semiconductor device, for operation in a range of temperatures below 100.degree. K. The device has, in a silicon surface region where the channel of the device is formed, a low impurity concentration layer (between the source and drain regions of the device).

Abstract: In a homo-junction bipolar transistor suitable for a low temperature operation below 200 K. (particularly below 77 K.), the maximum value of the impurity concentration of an intrinsic base region is set to be at least 1.times.10.sup.18 /cm.sup.3 and the impurity concentration of an emitter region is set to a value lower than this maximum value. Thus, a base resistance can be reduced and a high speed operation becomes possible. Furthermore, bandgap narrowing develops in the intrinsic base region and a common-emitter current gain in the low temperature operation can be kept at a sufficient value. When this homo-junction bipolar transistor is formed together with complementary insulated gate field effect transistors on the surface of a semiconductor substrate, there can be obtained a Bi-CMOS device capable of a high speed operation even in the low temperature operation.

Abstract: Disclosed is an MOSIC including a plurality of silicon gate type MOSFET's in which, after polycrystalline silicon wirings are formed simultaneously with polycrystalline silicon gates, the electrodes contacted with the source and drain regions are made of polycrystalline silicon so as to be connected to the polycrystalline silicon wirings, thereby to prevent the shallow pn junctions of the source and drain regions from being destroyed by the contacts and to provide a high degree of integration to one silicon chip.

Abstract: In a homo-junction bipolar transistor suitable for a low temperature operation below 200.degree.K. (particularly below 77 K), the maximum value of the impurity concentration of an intrinsic base region is set to be at least 1.times.10.sup.18 /cm.sup.3. The impurity concentration of an emitter region is set to a value lower than this maximum value. Thus, a base resistance can be reduced and high speed operation becomes possible. Furthermore, bandgap narrowing develops in the intrinsic base region and a common-emitter current gain in the low temperature operation can be kept at a sufficient value. When this homo-junction bipolar transistor is formed together with complementary insulated gate field effect transistors on the surface of a semiconductor substrate, there can be obtained a Bi-CMOS device capable of a high speed operation even in the low temperature operation.

Abstract: In a defect relieving technology which replaces defective memory cells of a semiconductor memory device by spare memory cells, use is made of an associative memory. Address information of a defective memory cell is stored as a reference data of the associative memory, and new address information of a spare memory cell is written down as output data of the associative memory. A variety of improvements are made to the associative memory. For instance, a plurality of coincidence detection signal lines of the associative memory are divided into at least two groups, and one group among them is selected by switching means. Reference data of the associative memory comprises three values consisting of binary information of "0" and "1", and don't care value "X". The associative memory further includes a plurality of electrically programable non-volatile semiconductor memory elements.

Abstract: A semiconductor memory device is disclosed, in which a word line address translation unit, a data line address translation unit, a first spare memory and a second spare memory are provided in addition to a main memory to relieve a defective memory cell in the main memory. Spare word line address signals for selecting a spare word line on the first spare memory are written in the word line address translation unit, spare data line address signals for selecting a spare data line on the second spare memory are written in the data line address translation unit, and each of the word line address translation unit and the data line address translation unit is constructed of an ordinary semiconductor memory of the multi-bit output type.

Abstract: A static RAM memory is divided into a plurality of mats (12). Word lines (16) in each pair of mats are accessed by an x-decoder (14). Columns or bit lines are accessed by a y-decoder (20) which selectively connect pairs of bit lines (22) to common data bus segments (24). Transistors (60, 62) connect selected bit lines with a load during a write cycle to stabilize those bit lines and memory cells into which data is written. The x-decoders are connected with near word lines (16a) for addressing a near half of each mat and are operatively connected with remote word lines (16b) for addressing word lines in a remote half of each mat. In this manner, each mat is divided into two effective mats. The bit lines of all the effective mats within an actual mat are connected with the same output data bus segment. A pair of sensing amplifiers (32) is provided for each bit of memory which is accessed concurrently, e.g. eight bits, such that the high and low output of each flip-flop memory cell (18) are both amplified.

Abstract: A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

Abstract: A MOS memory is formed in a semiconductor bulk, whereas a barrier semiconductor layer is disposed at the boundary between a MOS memory portion and the semiconductor bulk in order to reduce the effect of undesirable carriers excited by .alpha.-particles. The barrier semiconductor layer is designed to permit operation of the memory at low temperature while reducing the incidence of soft errors due to .alpha.-particles.

Abstract: A semiconductor memory device is provided in which an electrode applied with the power supply voltage or the ground voltage is provided on an insulating layer over the drain and/or the gate of the MOS transistors constituting the memory cell of a static memory device, thereby to increasing the capacitance of the storing node of the memory cell. This semiconductor memory device significantly reduces the occurrence of soft errors.

Abstract: A semiconductor memory device having a memory plane defined by a plurality of memory cells, a decoder line for accessing the memory cells, a common data line on which a signal output from an accessed memory cell is collected, and a sense amplifier for amplifying the signal collected on the common data line. The sense amplifier has an amplifying circuit portion which is composed of a pair of common-collector type bipolar transistors supplied with the signal collected on the common data line as a differential input, and a plurality of MOS transistors for converting a change in current into a change in voltage. Each of the MOS transistors has a lightly-doped drain structure.