Abstract: A static random access memory cell in which capacitors are electrically connected to storage nodes, so that the memory cell will not suffer from soft error even when it is hit by alpha particles. The memory cell has MOS transistors, capacitors constituted by two polycrystalline silicon layers, and resistors constituted by a polycrystalline silicon layer, that are formed on a semiconductor substrate.

Abstract: Each of the memory cells in a SRAM includes two driver MOS transistors, two transfer gate MOS transistors and two load resistances. The gate electrode layers of the MOS transistors are formed from a first-level conductive layer provided on the surface of a semiconductor substrate. The source regions of the two driver MOS transistors in each memory cell are connected in common and further connected to a ground potential point through a second-level conductive layer. The two load resistances in each memory cell are formed from a third-level high-resistance material layer. The second-level conductive layer is formed from a low-resistance material layer. Thus the resistance of the sources of the two driver MOS transistors is lowered.

Abstract: Disclosed is an MOSIC including a plurality of silicon gate type MOSFET's in which, after the polycrystalline silicon wirings are formed simultaneously with polycrystalline silicon gates, electrodes contacted with the source and drain regions are made of polycrystalline silicon so as to be connected to the polycrystalline silicon wirings, thereby to prevent the shallow pn junctions of the source and drain regions from being destroyed by the contacts and to provide a high degree of integration to one silicon chip.

Abstract: A CMOS IC is formed on a semiconductor crystalline surface having a plane azimuth (110) or (023), or of a plane azimuth close thereto (plane azimuth substantially in parallel with the above-mentioned planes), in order to increase the speed of operation.At low temperatures, dependency of the carrier mobility upon the plane azimuth becomes more conspicuous as shown in FIG. 1, and the difference of mobility is amplified depending upon the planes. Therefore, employment of the above-mentioned crystalline planes helps produce a great effect when the CMOS device is to be operated at low temperature (e.g., 100.degree. K. or lower), and helps operate the device at high speeds.

Abstract: A semiconductor memory is provided with automatic refresh means including a timer, a refresh counter and a refresh buffer each formed on a semiconductor chip mounted with an asynchronous memory, for automatically performing a periodic refresh operation on the basis of a basic clock signal which is generated in response to the detection of a logical change in the output of the refresh counter. The automatic refresh counter includes means for performing one of a read operation and a write operation which are based upon a regular address signal asynchronous with the periodic refresh operation, in preference to the periodic refresh operation.

Abstract: Electric charge is supplied to a circuit node being in a charge storing state within a signal processor in response to a signal-processing commencing signal. The processor is operated in a low-temperature range, for example, in the range of temperature below 200K. By this structure, a leakage current is reduced, a high degree of integration equivalent to that of a dynamic circuit can be obtained, and the simplicity of a static circuit not requiring any complicated internal/external timing signals can be realized.

Abstract: A semiconductor memory device is proposed wherein at least an array comprising a plurality of memory cells each having at least one capacity, a select mechanism for specifying the position of each memory cell, data lines connected to said memory cells for transmitting the data and a data writing and a data reading mechanisms are provided.

Abstract: A semiconductor memory using a dynamic memory device, wherein a battery supplies a power source voltage and a substrate bias voltage when the memory is cut off from an external device, and a refresh control circuit changes in refresh timing of the memory device in accordance with the leakage current of the memory device. The power consumption of the memory can thus be reduced and the data can be kept for an extended period without an external power source.

Abstract: This invention relates to a protection device of a semiconductor device. The present invention can prevent the drop of a gate breakdown voltage due to miniaturization of a device without impeding the high speed performance of the circuit attached thereto. The invention improves the voltage that can be applied to the input terminal of the device by reducing the surface breakdown voltage of a surface breakdown type MOS transistor, which is a principal member of a protection device, and reducing the resistance after the breakdown. This can be accomplished, for example, by increasing the concentration of a region in which the MOS transistor is disposed, by reducing the depth of the region, and so forth.

Abstract: Disclosed is a semiconductor integrated circuit which comprises an n-type silicon substrate, a p-type well region having an opening at a part thereof, which is formed on the surface portion of the substrate, an MOS transistor formed in the p-type region and a resistance layer extended from the drain region of the MOS transistor to the opening of the p-type well region through a insulating film formed on the surface of the substrate, in which the drain region of the MOS transistor is electrically connected to the silicon substrate through the resistance layer so that a current is supplied to the MOS transistor.

Abstract: The present invention consists in a semiconductor integrated circuit device characterized in that a circuit programming wiring layer is formed on an insulating film which is provided on a semiconductor substrate, and that a light shielding protective mask material is deposited around the circuit programming wiring layer except a program part thereof, through an insulating film.

Abstract: A solid-state imager includes vertical CCD shift registers for transferring photogenerated signal charge packets produced by a group of photodiodes belonging to a first series, vertical CCD shift registers for transferring photogenerated signal charge packets produced by photodiodes belonging to a second series, a horizontal CCD shift register for receiving signal charge packets shifted through both the vertical shift registers and transferring them to an output circuit and a coupling circuit provided between the horizontal CCD shift register and both the vertical CCD shift registers, all the components being formed on a single semiconductor substrate.

Abstract: A nonvolatile memory in which at least one power supply element is carried with an integrated circuit chip containing the memory and connected to power supply terminals of the integrated circuit chip having a memory cell array in which a plurality of memory elements or memory circuits are arrayed.

Abstract: A solid-state imaging device is provided which employs CCDs as vertical shift registers and a horizontal shift register for vertically and horizontally scanning and reading out a large number of photoelectric elements arrayed in a two-dimensional plane. The imaging device is characterized in that the photoelectric elements of each column arranged between the vertical shift registers are alternately connected to the right and left vertical shift registers. This results in the resolution of the device being enhanced sharply.

Abstract: A semiconductor integrated circuit device is provided to include a vertical type MOSFET and a gate protection element for the MOSFET. The vertical type MOSFET is made up of a silicon layer of n-type conductivity formed on an n.sup.+ -type silicon substrate, a base region of p-type conductivity formed in the surface of the silicon layer of n-type conductivity, an n.sup.+ -type source region provided in the base region, and a gate electrode formed on a portion of the base region through a gate insulating film. The silicon substrate serves as the drain. The gate protection element is formed of a polycrystalline silicon layer which is provided on the base region through an insulating film and includes at least one pn junction. By virtue of forming the gate protection element over the base region rather than directly over the substrate, a more stable operation is achieved.

Abstract: A programmable semiconductor integrated circuitry including a circuit programming element is disclosed. The circuit programming element can be activated in a short-circuit mode by the irradiation of a laser or electron beam or by ion implantation so that it is converted from its original nonconductive state into a conductive or conductable state, thereby providing electrical connection between circuits and/or circuit elements of the integrated circuitry for a desired circuit programming such as circuit creation, circuit conversion or circuit substitution.

Abstract: A semiconductor device including at least a resistance element formed of polycrystalline silicon having a high resistivity. An electrode is provided on the high resistance polycrystalline silicon region with a silicon dioxide film and a silicon nitride film being interposed therebetween. The electrode is coupled to the ground potential. In this manner, high stability is obtained in the behavior of the resistance element inasmuch as the formation of a parasitic MOS device under said high resistance region is suppressed, and the threshold voltage of any such MOS device is made raised.

Abstract: This invention relates to a tri-state type driver circuit in which any one of the three possible output signals of "float", "on", or "off" is produced at high speed even when an output terminal is accompanied with a great load. The tri-state type driver circuit comprises an output inverter circuit which employs a bipolar transistor as a load thereof and a MOS-FET as a driver thereof, a first logical circuit which is coupled to an input terminal of the bipolar transistor, which first logical circuit is made up of a C-MOS circuit receiving an external select signal and a C-MOS circuit having an input signal transmitted thereto and whose output can be specified by the external select signal, and a second logical circuit which is coupled to an input terminal of the MOS-FET, which second logical circuit is made up of a C-MOS circuit receiving the external select signal and a C-MOS circuit having the input signal transmitted thereto.

Abstract: On the surface of an insulating film formed on the surface of a semiconductor substrate on which an MOS type semiconductor device to be protected is formed, there are formed a first polycrystal silicon member having input and output terminals and a resistivity lower than 1 K.OMEGA./.quadrature. and a second polycrystalline silicon member having a resistivity lower than 1 K.OMEGA./.quadrature. and being maintained at a fixed potential. This second polycrystalline silicon member faces at least a part of the first silicon member with polycrystalline silicon of a resistivity higher than 100 K.OMEGA./.quadrature. interposed therebetween. The input terminal of the first polycrystalline silicon member is connected to an input pad of the MOS type semiconductor device to be protected and the output terminal of the first polycrystalline silicon member is connected to an input gate of the semiconductor device to be protected.

Abstract: In a semiconductor integrated circuit having polycrystalline silicon interconnections and metal interconnections, a low resistance layer, containing impurities to a high concentration for the polycrystalline silicon interconnections, is formed in predetermined parts of an undoped polycrystalline silicon layer which is deposited on a first insulator film on a semiconductor substrate, a second insulator film is deposited on the polycrystalline silicon layer under the state under which the undoped parts are left at least around through-holes to be formed, and the metal interconnections at least parts of which run in a direction intersecting the polycrystalline silicon interconnections are provided on the second insulator film, the necessary contacts between the metal interconnections and the polycrystalline silicon interconnections being made through the through-holes provided in the second insulator film in correspondence with the intersecting parts of both the interconnections.