Abstract: An electron device comprising (i) a semiconductor element which includes a semiconductor region A of a first conductivity type, a semiconductor region B of a second conductivity type adjoining the region A, and a semiconductor region C of the second conductivity type adjoining the region A and isolated from the region B by the region A, and in which on a surface extending from the region B via the region A to the region C, a gate electrode is provided through an insulating film, (ii) means for holding a potential of the gate electrode so that a potential of minority carriers in a surface portion of the region A underneath the gate electrode may become lower than a potential in an inner portion of the region A, (iii) means for applying a forward bias voltage between the region A and the region B, and (iv) means for applying to the region C a potential by which a potential for the minority carriers becomes lower in the region C than in the region B.

Abstract: A MOS-FET (Metal-Oxide-Semiconductor Field Effect Transistor) comprises a semiconductor body, source and drain regions disposed in the body at portions separated from each other, a second semiconductor region having a higher impurity concentration than that of the body, formed by ion implantation in the body between the source and drain regions, a first semiconductor region having a lower impurity concentration than that of the second semiconductor region but a higher impurity concentration than that of the body, and having an opposite conductivity type to that of the second semiconductor region, formed by ion implantation, so that the second semiconductor region is very thin, and which has a very small amount of a minute current, that is a tailing current.

Abstract: An enhancement-type and a depletion-type metal-insulator-semiconductor field effect transistor are formed on a common substrate of silicon and are electrically isolated from each other by a plurality of layers including, for example, a first layer of SiO.sub.2, a second layer of Al.sub.2 O.sub.3 capable of inducing holes in the surface portion of the substrate, and a third layer of SiO.sub.2, and the relation between the thicknesses of these layers is suitably selected for attaining the satisfactory isolation between these transistors.