Abstract: Disclosed is an internal combustion engine, which has a geometric compression ratio of 13.0 or greater, and a combustion chamber (4) configured to satisfy a condition of S/V2?0.12 (mm?1) when a radius r of a hypothetical sphere (IS) with its center at an ignition point (CP) of a spark plug (3) is set to satisfy a condition of V2=0.15×V1, where: S (mm2) is an area of an interference surface between the hypothetical sphere (IS) and an inner wall of the combustion chamber (4) in a state when a piston (30) is at its top dead center position; V1 (mm3) is a volume of the combustion chamber 4 in the state when the piston (30) is at the top dead center position; and V2 (mm3) is a volume of a non-interference part of the hypothetical sphere (IS) which is free of interference with the inner wall of the combustion chamber (4) when the piston (30) is at the top dead center position. The internal combustion engine of the present invention can more reliably improve fuel economy.

Abstract: Disclosed is an internal combustion engine (A), which has a valve overlap period (T) during which an intake valve (1) and an exhaust valve (2) are opened, and a geometric compression ratio of 13.0 or greater. The engine (A) is designed to satisfy, at a center timing (Tc) of the valve overlap period (T), a conditional expression: S1?S2, where S1 is a cross-sectional area of a combustion chamber (4) taken along any selected one of a plurality of mutually parallel hypothetical cutting-planes (IP) each of which extends parallel to a linear reciprocating direction (d1 or d2) of at least one of the intake and exhaust valves (1, 2) and passes through a valve head (1a or 2a) of the at least one of the valves (1, 2), and S2 is an effective opening area defined between the valve head (1a or 2a) and a corresponding valve seat (11a or 12a) in a region on an outward side of the combustion chamber (4) relative to the selected hypothetical cutting-plane (IP).

Abstract: A spark-ignition gasoline engine having at least a spark plug, the engine including an engine body having a geometrical compression ratio set at 14 or more, and an intake valve and an exhaust valve provided, respectively, in intake and exhaust ports connected to each of a plurality of cylinders of the engine body. The intake and exhaust valves are adapted to open and close corresponding respective ones of the intake and exhaust ports. The engine further includes an operation-state detector adapted to detect an operation state of the engine body and a control system adapted, based on detection of the operation-state detector, to perform at least an adjustment control of an ignition timing of the spark plug, the control system being operable, when an engine operation zone is a high-load operation zone including a wide open throttle region within at least a low speed range, to retard the ignition timing to a point within a predetermined stroke range just after a top dead center of a compression stroke.

Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

Abstract: Disclosed is a spark-ignition gasoline engine, which comprises control means operable, when an engine operation zone is a high-load operation zone including a WOT region within at least a low speed range, to adjust a closing timing of an intake valve in such a manner as to maintain an effective compression ratio at 13 or more, and retard an ignition timing to a point within a predetermined stroke range just after a top dead center of a compression stroke, wherein the effective compression ratio is calculated based on an intake-valve closing timing defined by a valve lift amount of 1 mm. The present invention can provide a spark-ignition gasoline engine having both a low-cost performance and a high engine-power performance even in a high-load operation zone (particularly WOT region) in a low speed range.

Abstract: A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.

Abstract: A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.

Abstract: This invention relates to a combustion chamber structure for a spark-ignition engine, which comprises a combustion chamber defined between a bottom surface of a cylinder head and a top surface of a piston in such a manner that the bottom surface of the cylinder head serves as a ceiling wall thereof, and a spark plug having a sparking end protruding from the ceiling wall into the combustion chamber. In this combustion chamber structure, when the piston is at a top dead center, a principal space of the combustion chamber is comprised of a first combustion space around the sparking end of the spark plug and a second combustion space around a circumference of a cylinder bore. Further, the first combustion space and the second combustion space are communicated with each other through a small interspace zone where an interspace between the ceiling wall and the top surface of the piston is narrowed. The combustion chamber structure makes it possible to increase compression ratio in a practically effective manner.

Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

Abstract: Disclosed is a spark-ignition gasoline engine, which comprises control means operable, when an engine operation zone is a high-load operation zone including a WOT region within at least a low speed range, to adjust a closing timing of an intake valve in such a manner as to maintain an effective compression ratio at 13 or more, and retard an ignition timing to a point within a predetermined stroke range just after a top dead center of a compression stroke, wherein the effective compression ratio is calculated based on an intake-valve closing timing defined by a valve lift amount of 1 mm. The present invention can provide a spark-ignition gasoline engine having both a low-cost performance and a high engine-power performance even in a high-load operation zone (particularly WOT region) in a low speed range.

Abstract: For the purpose of improving the fuel efficiency by lean combustion and enhancing the fuel efficiency improvement effects by performing compression ignition efficiently in some cylinders, a multi-cylinder spark ignition engine is constructed such that exhaust gas, that is exhausted from preceding cylinders 2A, 2D on the exhaust stroke side among pairs of cylinders whose exhaust stroke and intake stroke overlap in a low load, low rotational speed region, is directly introduced through an inter-cylinder gas passage 22 into following cylinders 2B, 2C on the intake stroke side and only gas exhausted from the following cylinders 2B, 2C is fed to an exhaust passage 20, which is provided with a three-way catalyst 24.

Abstract: This invention relates to a combustion chamber structure for a spark-ignition engine, which comprises a combustion chamber defined between a bottom surface of a cylinder head and a top surface of a piston in such a manner that the bottom surface of the cylinder head serves as a ceiling wall thereof, and a spark plug having a sparking end protruding from the ceiling wall into the combustion chamber. In this combustion chamber structure, when the piston is at a top dead center, a principal space of the combustion chamber is comprised of a first combustion space around the sparking end of the spark plug and a second combustion space around a circumference of a cylinder bore. Further, the first combustion space and the second combustion space are communicated with each other through a small interspace zone where an interspace between the ceiling wall and the top surface of the piston is narrowed. The combustion chamber structure makes it possible to increase compression ratio in a practically effective manner.

Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

Abstract: A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.

Abstract: A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.

Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

Abstract: A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.

Abstract: A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.

Abstract: In a partial load range of the engine, control of the flowing state of sucked and discharged gas is executed between a pair of cylinders, an exhaust stroke of one of the cylinders overlapping with an intake stroke of the other, so that burnt gas discharged from preceding cylinders 2A, 2D on the exhaust-stroke side is introduced, in a state where it has been discharged, through an inter-cylindrical gas passage 22 into following cylinders 2B, 2C on the intake stroke side. In a higher load range than the partial load range, control is executed so that a fresh-air introducing valve 18 disposed in a fresh-air introduction passage of the following cylinders 2B, 2C is opened, both the burnt gas and fresh air are introduced into the following cylinders 2B, 2C, and fuel is supplied to conduct combustion in the following cylinders 2B, 2C.

Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.