Patents by Inventor Toshiaki Nishimoto

Toshiaki Nishimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of making tunnel EEPROM
    Patent number: 5153144
    Abstract: An EEPROM (Electrically Erasable Programmable Read Only Memory) has a structure in which the corners of a floating gate electrode of each memory cell MISFET near the source region thereof are rounded.The EEPROM is manufactured by a method characterized in that the ions of an impurity at a high dose are implanted in self-alignment with the floating gate electrode and control gate electrode of the memory cell MISFET so as to form the source and drain regions thereof, whereupon an oxidizing treatment is carried out.
    Type: Grant
    Filed: November 18, 1991
    Date of Patent: October 6, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiro Komori, Satoshi Meguro, Toshiaki Nishimoto, Hitoshi Kume, Hideaki Yamamoto
  • Non-volatile semiconductor memory device erasing operation
    Patent number: 4996571
    Abstract: The invention relates to a tunnel erasing device for a non-volatile semiconductor memory device comprising a source region and a drain region, a floating gate electrode having a part superposed on at least one of them through a gate insulating layer, and a control gate electrode disposed over the floating gate electrode through an interlayer insulating layer and is characterized as having a preliminary erasing operation in which a voltage is so applied to at least one of the source or drain region, with the control gate electrode grounded, that a relatively lower voltage than a predetermined voltage is applied preliminarily prior to applying thereto the predetermined voltage.
    Type: Grant
    Filed: July 6, 1989
    Date of Patent: February 26, 1991
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Hitoshi Kume, Yoshiaki Kamigaki, Tetsuo Adachi, Toshihisa Tsukada, Kazuhiro Komori, Toshiaki Nishimoto, Tadashi Muto, Toshiko Koizumi
  • Semiconductor memory device
    Patent number: 4972371
    Abstract: An EEPROM in which a memory cell is constituted by a floating gate electrode, a control gate electrode, a first semiconductor region provided in a main surface portion of the semiconductor substrate on an end side of the gate electrodes to which the data line is connected, and a second semiconductor region provided in a different main surface portion of the semiconductor substrate on an opposing end side of the gate electrodes to which the grounding line is connected. The drain is used differently depending upon the operations for writing the data, reading the data and erasing the data. The impurity concentration in the first semiconductor region is selected to be lower than that of the second semiconductor region, in order to improve writing and erasing characteristics as well as to increase the reading speed.
    Type: Grant
    Filed: June 7, 1988
    Date of Patent: November 20, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiro Komori, Takaaki Hagiwara, Satoshi Meguro, Toshiaki Nishimoto, Takeshi Wada, Kiyofumi Uchibori, Tadashi Muto, Hitoshi Kume, Hideaki Yamamoto, Tetsuo Adachi, Toshihisa Tsukada, Toshiko Koizumi