Abstract: A control device switches an engine between normal operation mode and special operation mode. In the normal operation mode, an independent cylinder configuration is formed to produce combustion independently in individual cylinders. In the special operation mode, a two-cylinder interconnect configuration is formed so that burned gas discharged from preceding cylinders currently in an exhaust stroke is introduced into following cylinders currently in an intake stroke through intercylinder gas channels, a lean mixture having a high air-fuel ratio is combusted in the preceding cylinders, and a mixture produced by supplying fuel to the burned gas is combusted in the following cylinders.

Abstract: A control device for a multicylinder spark-ignition engine includes a flow path switching unit for switching intake and exhaust flow paths between a two-cylinder interconnect configuration and an independent cylinder configuration and an air-fuel ratio control unit. In a low-load, low-speed operating range, the flow path switching unit switches the engine to the two-cylinder interconnect configuration, and the air-fuel ratio control unit produces a lean mixture having an air-fuel ratio larger than the stoichiometric air-fuel ratio by a specific amount in preceding cylinders by injecting fuel thereinto and an air-fuel ratio approximately equal to the stoichiometric air-fuel ratio in following cylinders by supplying fuel together with burned gas of a lean mixture state discharged from the preceding cylinders into the following cylinders to perform combustion in special operation mode.

Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

Abstract: A control device switches an engine between normal operation mode and special operation mode. In the normal operation mode, an independent cylinder configuration is formed to produce combustion independently in individual cylinders. In the special operation mode, a two-cylinder interconnect configuration is formed so that burned gas discharged from preceding cylinders currently in an exhaust stroke is introduced into following cylinders currently in an intake stroke through intercylinder gas channels, a lean mixture having a high air-fuel ratio is combusted in the preceding cylinders, and a mixture produced by supplying fuel to the burned gas is combusted in the following cylinders.

Abstract: A valve driving device including a tappet assembly adapted to slide in a tappet guide hole to drive a valve and including a high-speed center tappet and low-speed side tappet; and a high-speed center cam and a low-speed side cam provided corresponding to the center tappet and the side tappet. A depression is formed which is depressed from a base circle to roughly the same profile as a shaft section of the camshaft so that the cam portion over a predetermined angle range where a cam nose section is not formed in the centrally located center cam is smaller than the base circles of the outside located side cams in profile.

Abstract: For the purpose of improving the fuel efficiency by lean combustion and enhancing the fuel efficiency improvement effects by performing compression ignition efficiently in some cylinders, a multi-cylinder spark ignition engine is constructed such that exhaust gas, that is exhausted from preceding cylinders 2A, 2D on the exhaust stroke side among pairs of cylinders whose exhaust stroke and intake stroke overlap in a low load, low rotational speed region, is directly introduced through an inter-cylinder gas passage 22 into following cylinders 2B, 2C on the intake stroke side and only gas exhausted from the following cylinders 2B, 2C is fed to an exhaust passage 20, which is provided with a three-way catalyst 24.

Abstract: In the semiconductor integrated circuit device, an AND-type flash memory is formed on a substrate in which stripe-like element separation regions 5 are formed and active regions L sandwiched between the element separation regions 5 are formed like stripes. A silicon monocrystal substrate containing nitrogen or carbon is used as the semiconductor substrate, to reduce dislocation defects and junction leakages so that the reliability and yield are improved.

Abstract: A simple and easy method for exercising quality control over memory cell inter-layer dielectric film within a short period of time, using a memory array or single memory formed in the scribe area, without stressing nonvolatile semiconductor memory cells and a method of manufacturing a nonvolatile semiconductor memory device; whereby a single nonvolatile memory is formed in an area other than a chip area on a semiconductor wafer and used after completion of a wafer manufacturing process to perform an inter-layer dielectric film quality control process for evaluating the write saturation characteristic, cut out nondefective chips only, and conduct a plastic molding process, achieving an increased yield after chip cutting.

Abstract: A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.

Abstract: A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.

Abstract: A valve driving device including a tappet assembly adapted to slide in a tappet guide hole to drive a valve and including a high-speed center tappet and low-speed side tappet; and a high-speed center cam and a low-speed side cam provided corresponding to the center tappet and the side tappet. A depression is formed which is depressed from a base circle to roughly the same profile as a shaft section of the camshaft so that the cam portion over a predetermined angle range where a cam nose section is not formed in the centrally located center cam is smaller than the base circles of the outside located side cams in profile.

Abstract: A control device for a multicylinder spark-ignition engine includes a flow path switching unit for switching intake and exhaust flow paths between a two-cylinder interconnect configuration and an independent cylinder configuration and an air-fuel ratio control unit. In a low-load, low-speed operating range, the flow path switching unit switches the engine to the two-cylinder interconnect configuration, and the air-fuel ratio control unit produces a lean mixture having an air-fuel ratio larger than the stoichiometric air-fuel ratio by a specific amount in preceding cylinders by injecting fuel thereinto and an air-fuel ratio approximately equal to the stoichiometric air-fuel ratio in following cylinders by supplying fuel together with burned gas of a lean mixture state discharged from the preceding cylinders into the following cylinders to perform combustion in special operation mode.

Abstract: In a partial load range of the engine, control of the flowing state of sucked and discharged gas is executed between a pair of cylinders, an exhaust stroke of one of the cylinders overlapping with an intake stroke of the other, so that burnt gas discharged from preceding cylinders 2A, 2D on the exhaust-stroke side is introduced, in a state where it has been discharged, through an inter-cylindrical gas passage 22 into following cylinders 2B, 2C on the intake stroke side. In a higher load range than the partial load range, control is executed so that a fresh-air introducing valve 18 disposed in a fresh-air introduction passage of the following cylinders 2B, 2C is opened, both the burnt gas and fresh air are introduced into the following cylinders 2B, 2C, and fuel is supplied to conduct combustion in the following cylinders 2B, 2C.

Abstract: There was a problem that sharpening of a substrate and localized increase in the thickness of a gate oxide film become more remarkable as the thickness of the gate oxide film is increased to degrade the gate withstand voltage at the surface edge of shallow groove isolation structure. In the present invention, a bird's beak is disposed at the surface edge of a shallow isolation structure GROX11 just below gate electrode POLY11 and in contact with the gate insulation film HOX1 to form the gate insulation film HOX1 previously. This can ensure normal gate withstand voltage of the MOS transistor and favorable device isolation withstand voltage and increased integration degree simultaneously.

Abstract: In the semiconductor integrated circuit device, an AND-type flash memory is formed on a substrate in which stripe-like element separation regions 5 are formed and active regions L sandwiched between the element separation regions 5 are formed like stripes. A silicon monocrystal substrate containing nitrogen or carbon is used as the semiconductor substrate, to reduce dislocation defects and junction leakages so that the reliability and yield are improved.

Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

Abstract: In the semiconductor integrated circuit device, an AND-type flash memory is formed on a substrate in which stripe-like element separation regions 5 are formed and active regions L sandwiched between the element separation regions 5 are formed like stripes. A silicon monocrystal substrate containing nitrogen or carbon is used as the semiconductor substrate, to reduce dislocation defects and junction leakages so that the reliability and yield are improved.

Abstract: A simple and easy method for exercising quality control over memory cell inter-layer dielectric film within a short period of time, using a memory array or single memory formed in the scribe area, without stressing nonvolatile semiconductor memory cells and a method of manufacturing a nonvolatile semiconductor memory device; whereby a single nonvolatile memory is formed in an area other than a chip area on a semiconductor wafer and used after completion of a wafer manufacturing process to perform an inter-layer dielectric film quality control process for evaluating the write saturation characteristic, cut out nondefective chips only, and conduct a plastic molding process, achieving an increased yield after chip cutting.

Abstract: A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.

Abstract: An EEPROM (Electrically Erasable Programmable Read Only Memory) has a structure in which the corners of a floating gate electrode of each memory cell MISFET near the source region thereof are rounded. The EEPROM is manufactured by a method characterized in that the ions of an impurity at a high dose are implanted in self-alignment with the floating gate electrode and control gate electrode of the memory cell MISFET so as to form the source and drain regions thereof, whereupon an oxidizing treatment is carried out.