Patents by Inventor Toshifumi Hashimoto
Toshifumi Hashimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200395341Abstract: A semiconductor memory device includes a memory chip. The memory chip includes a first region including a plurality of first memory cells and second memory cells, a second region different from the first region, a plurality of first word lines stacked apart from each other in a first direction in the first and second regions, a first pillar including a first semiconductor layer extending through the first word lines, and a first insulator layer provided between the first semiconductor layer and the first word lines, in the first region, the first memory cells being located at intersections of the first pillar with the first word lines, a first bonding pad in the second region, and a first transistor between the first word lines and the first bonding pad, and connected between one of the first word lines and the first bonding pad, in the second region.Type: ApplicationFiled: February 26, 2020Publication date: December 17, 2020Inventors: Hiroshi MAEJIMA, Toshifumi HASHIMOTO, Takashi MAEDA, Masumi SAITOH, Tetsuaki UTSUMI
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Publication number: 20200378055Abstract: The present disclosure relates to a clothes dryer capable of reducing pressure loss of air due to a lint removal device. The clothes dryer includes a case, a drum rotatably supported inside the case, an air supply port configured to guide air into the drum, an exhaust port configured to guide air inside the drum to the outside of the drum, an exhaust duct configured to guide air passed through the exhaust port to the air supply port, a connecting duct connecting the exhaust port and the exhaust duct, and a lint removal device configured to remove lint in the air passed through the exhaust port, wherein the lint removal device is disposed inside the exhaust duct and configured to communicate with the connecting duct.Type: ApplicationFiled: November 23, 2018Publication date: December 3, 2020Inventors: Shigenori HATO, Toshifumi HASHIMOTO, Hitoshi MINAI
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Publication number: 20200286563Abstract: A semiconductor memory device includes a first memory transistor, a first wiring connected to a gate electrode of the first memory transistor, a connection transistor connected to the first wiring, and a second wiring connected to the connection transistor. In a first write operation for the first memory transistor, during a first time period, a voltage of the first wiring increases to a first voltage and a voltage of the second wiring increases to a second voltage larger than the first voltage, and during a second time period directly after the first time period and directly after the connection transistor is turned ON, the voltage of the first wiring increases to a third voltage larger than the first voltage and smaller than the second voltage, and the voltage of the second wiring decreases to a fourth voltage larger than the first voltage and smaller than the second voltage.Type: ApplicationFiled: August 20, 2019Publication date: September 10, 2020Inventor: Toshifumi HASHIMOTO
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Patent number: 10679713Abstract: A semiconductor storage device comprises a memory block including first and second memory cells, first and second word lines electrically connected to the first and second memory cells, respectively, first and second booster circuits, and a control circuit. During a read operation in which the first word line is a selected word line, the control circuit controls the first booster circuit to start boosting the output voltage thereof before a target block address associated with the read command is determined, causes the output voltage of the first booster circuit to be supplied to the first and second word lines, controls the second booster circuit to start boosting the output voltage thereof, and causes the output voltage of the second booster circuit, instead of the output voltage of the first booster circuit, to be supplied to the first word line.Type: GrantFiled: April 29, 2019Date of Patent: June 9, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Sanad Bushnaq, Toshifumi Hashimoto
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Patent number: 10643693Abstract: A semiconductor memory device includes a first memory cell array including a first memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a second memory cell array including a second memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a first word line electrically connected to a gate of the first memory cell, and a second word line electrically connected to a gate of the second memory cell. In a read operation, at least first, second, and third voltages are applied successively to both the first word line and the second word line to read a first page including the first bit of the first memory cell and a second page including the second bit of the second memory cell.Type: GrantFiled: October 16, 2019Date of Patent: May 5, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Weihan Wang, Toshifumi Hashimoto, Noboru Shibata
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Publication number: 20200051622Abstract: A semiconductor memory device includes a first memory cell array including a first memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a second memory cell array including a second memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a first word line electrically connected to a gate of the first memory cell, and a second word line electrically connected to a gate of the second memory cell. In a read operation, at least first, second, and third voltages are applied successively to both the first word line and the second word line to read a first page including the first bit of the first memory cell and a second page including the second bit of the second memory cell.Type: ApplicationFiled: October 16, 2019Publication date: February 13, 2020Inventors: Weihan WANG, Toshifumi HASHIMOTO, Noboru SHIBATA
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Publication number: 20190383296Abstract: A vacuum pump comprises: a rotor; a stator; a rolling bearing configured to support a rotor shaft provided at the rotor; and a vibration sensor configured to detect vibration of the rolling bearing.Type: ApplicationFiled: May 2, 2019Publication date: December 19, 2019Inventors: Toshifumi HASHIMOTO, Nobuhiko MORIYAMA
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Patent number: 10490269Abstract: A semiconductor memory device includes a first memory cell array including a first memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a second memory cell array including a second memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a first word line electrically connected to a gate of the first memory cell, and a second word line electrically connected to a gate of the second memory cell. In a read operation, at least first, second, and third voltages are applied successively to both the first word line and the second word line to read a first page including the first bit of the first memory cell and a second page including the second bit of the second memory cell.Type: GrantFiled: October 10, 2018Date of Patent: November 26, 2019Assignee: Toshiba Memory CorporationInventors: Weihan Wang, Toshifumi Hashimoto, Noboru Shibata
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Publication number: 20190345662Abstract: A clothes dryer comprises a drum to stir clothes accommodated therein, an exhaust duct configured to discharge air inside the drum, a lint removing device including a filter to remove lint in air discharged to the exhaust duct, and a foreign-substance separating plate installed between the exhaust duct and the lint removing device to separate solid foreign substances in the air discharged to the exhaust duct.Type: ApplicationFiled: January 22, 2018Publication date: November 14, 2019Inventors: Shigenori HATO, Toshifumi HASHIMOTO, Yuji AOSHIMA, Hitoshi MINAI
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Publication number: 20190252031Abstract: A semiconductor storage device comprises a memory block including first and second memory cells, first and second word lines electrically connected to the first and second memory cells, respectively, first and second booster circuits, and a control circuit. During a read operation in which the first word line is a selected word line, the control circuit controls the first booster circuit to start boosting the output voltage thereof before a target block address associated with the read command is determined, causes the output voltage of the first booster circuit to be supplied to the first and second word lines, controls the second booster circuit to start boosting the output voltage thereof, and causes the output voltage of the second booster circuit, instead of the output voltage of the first booster circuit, to be supplied to the first word line.Type: ApplicationFiled: April 29, 2019Publication date: August 15, 2019Inventors: Sanad BUSHNAQ, Toshifumi HASHIMOTO
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Patent number: 10352327Abstract: A vacuum pump includes: a rotor that is rotated to perform evacuation; a pump disassembly detection circuit that detects a disassembled state in which the vacuum pump is disassembled; and a pump operation prohibition circuit that prohibits rotary drive of the rotor when the pump operation prohibition circuit determines that the pump disassembly detection circuit has detected the disassembled state.Type: GrantFiled: December 19, 2011Date of Patent: July 16, 2019Assignee: SHIMADZU CORPORATIONInventors: Masaki Ohfuji, Toshifumi Hashimoto, Shingo Tanaka
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Patent number: 10325667Abstract: A semiconductor storage device includes a word line and a wiring, a first transistor controlled to connect the word line to the wiring, a first booster circuit configured to boost an output voltage thereof to a first voltage, a second transistor controlled to connect the first booster circuit to the wiring, and a control circuit configured to control the first booster circuit, and the first and second transistors during a read operation. During the read operation, the control circuit controls the first booster circuit to start boosting its output voltage to the first voltage while controlling the second transistor to connect the output of the first booster circuit to the wiring so that a voltage of the wiring rises together with the output voltage. After the output voltage has reached the first voltage, the control circuit controls the first transistor to connect the word line to the wiring.Type: GrantFiled: March 1, 2018Date of Patent: June 18, 2019Assignee: Toshiba Memory CorporationInventors: Sanad Bushnaq, Toshifumi Hashimoto
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Publication number: 20190080776Abstract: A semiconductor storage device includes a word line and a wiring, a first transistor controlled to connect the word line to the wiring, a first booster circuit configured to boost an output voltage thereof to a first voltage, a second transistor controlled to connect the first booster circuit to the wiring, and a control circuit configured to control the first booster circuit, and the first and second transistors during a read operation. During the read operation, the control circuit controls the first booster circuit to start boosting its output voltage to the first voltage while controlling the second transistor to connect the output of the first booster circuit to the wiring so that a voltage of the wiring rises together with the output voltage. After the output voltage has reached the first voltage, the control circuit controls the first transistor to connect the word line to the wiring.Type: ApplicationFiled: March 1, 2018Publication date: March 14, 2019Inventors: Sanad BUSHNAQ, Toshifumi HASHIMOTO
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Publication number: 20190043568Abstract: A semiconductor memory device includes a first memory cell array including a first memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a second memory cell array including a second memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a first word line electrically connected to a gate of the first memory cell, and a second word line electrically connected to a gate of the second memory cell. In a read operation, at least first, second, and third voltages are applied successively to both the first word line and the second word line to read a first page including the first bit of the first memory cell and a second page including the second bit of the second memory cell.Type: ApplicationFiled: October 10, 2018Publication date: February 7, 2019Inventors: Weihan WANG, Toshifumi HASHIMOTO, Noboru SHIBATA
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Patent number: 10121536Abstract: A semiconductor memory device includes a first memory cell array including a first memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a second memory cell array including a second memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a first word line electrically connected to a gate of the first memory cell, and a second word line electrically connected to a gate of the second memory cell. In a read operation, at least first, second, and third voltages are applied successively to both the first word line and the second word line to read a first page including the first bit of the first memory cell and a second page including the second bit of the second memory cell.Type: GrantFiled: November 8, 2016Date of Patent: November 6, 2018Assignee: Toshiba Memory CorporationInventors: Weihan Wang, Toshifumi Hashimoto, Noboru Shibata
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Publication number: 20170365335Abstract: A semiconductor memory device includes a first memory cell array including a first memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a second memory cell array including a second memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a first word line electrically connected to a gate of the first memory cell, and a second word line electrically connected to a gate of the second memory cell. In a read operation, at least first, second, and third voltages are applied successively to both the first word line and the second word line to read a first page including the first bit of the first memory cell and a second page including the second bit of the second memory cell.Type: ApplicationFiled: November 8, 2016Publication date: December 21, 2017Inventors: Weihan WANG, Toshifumi HASHIMOTO, Noboru SHIBATA
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Publication number: 20170249994Abstract: A semiconductor memory device includes a plurality of string units, including first and second string units in a first block, third and fourth string units in a second block, each of the string units including a plurality of serially connected memory cells between first and second select transistors, and first through fourth select gate lines. The first select gate line is commonly connected to gates of the first select transistors of the first and third string units. The second select gate line is commonly connected to gates of the first select transistors of the second and fourth string units. The third select gate line is commonly connected to gates of the second select transistors of the first and fourth string units. The fourth select gate line is commonly connected to gates of the second select transistors of the second string unit and another string unit.Type: ApplicationFiled: August 10, 2016Publication date: August 31, 2017Inventor: Toshifumi HASHIMOTO
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Patent number: 9679662Abstract: A memory device includes a semiconductor pillar, a first memory cell that includes a first memory film between a first word line and a side surface of the semiconductor pillar, a second memory cell that includes a second memory film between a second word line and the side surface of the semiconductor pillar, and a control circuit configured to carry out first and second operations on the first memory cell and the second memory cell during a reading operation. During the first operation, a read voltage is applied to the first word line and a read pass voltage is applied to the second word line, and during the second operation following the first operation, a first voltage is applied to the second word line, such that a potential of the second word line is lower than a potential of the semiconductor pillar.Type: GrantFiled: August 10, 2016Date of Patent: June 13, 2017Assignee: Kabushiki Kaisha ToshibaInventor: Toshifumi Hashimoto
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Patent number: 9672918Abstract: A semiconductor memory includes a first selection transistor and a second selection transistor on one end of a memory string. The first selection transistor includes a channel region in a semiconductor substrate, a channel region in a semiconductor pillar, and a gate electrode connected to a first line. The second selection transistor includes a channel region in the semiconductor pillar and a gate electrode connected to a second line. The first line is connected to a first voltage circuit, and the second line is connected to a second voltage circuit.Type: GrantFiled: February 27, 2015Date of Patent: June 6, 2017Assignee: kabushiki Kaisha ToshibaInventor: Toshifumi Hashimoto
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Publication number: 20170076814Abstract: A memory device includes a word line above a semiconductor substrate, a semiconductor pillar extending through the word line in a direction crossing a surface of the semiconductor substrate, a memory cell at an intersection of the word line and the semiconductor pillar and having a gate electrically connected to the word line, a bit line electrically connected to a first end of the memory cell, a source line electrically connected to a second end of the memory cell, and a controller that controls a write operation on the memory cell, the write operation including a program operation followed by a verify operation. During the verify operation on the memory cell, the semiconductor pillar is charged after performing a read operation on the memory cell.Type: ApplicationFiled: June 6, 2016Publication date: March 16, 2017Inventors: Toshifumi HASHIMOTO, Takeshi NAKANO