Abstract: A memory device includes a word line above a semiconductor substrate, a semiconductor pillar extending through the word line in a direction crossing a surface of the semiconductor substrate, a memory cell at an intersection of the word line and the semiconductor pillar and having a gate electrically connected to the word line, a bit line electrically connected to a first end of the memory cell, a source line electrically connected to a second end of the memory cell, and a controller that controls a write operation on the memory cell, the write operation including a program operation followed by a verify operation. During the verify operation on the memory cell, the semiconductor pillar is charged after performing a read operation on the memory cell.

Abstract: A semiconductor memory device includes first and second plugs formed on a semiconductor substrate, a word line between the first and second plugs and above the semiconductor substrate, a first semiconductor pillar extending above the semiconductor substrate through the word line, a second semiconductor pillar extending above the semiconductor substrate through the word line, a first bit line electrically connected to the first semiconductor pillar, and a second bit line electrically connected to the second semiconductor pillar. When writing same data in a first memory cell, which is electrically connected to the first bit line, and a second memory cell, which is electrically connected to the second bit line, a first voltage is applied to the first bit line and a second voltage that is different from the first voltage is applied to the second bit line.

Abstract: A semiconductor memory device includes first and second plugs formed on a semiconductor substrate, a word line between the first and second plugs and above the semiconductor substrate, a first semiconductor pillar extending above the semiconductor substrate through the word line, a second semiconductor pillar extending above the semiconductor substrate through the word line, a first bit line electrically connected to the first semiconductor pillar, and a second bit line electrically connected to the second semiconductor pillar. When writing same data in a first memory cell, which is electrically connected to the first bit line, and a second memory cell, which is electrically connected to the second bit line, a first voltage is applied to the first bit line and a second voltage that is different from the first voltage is applied to the second bit line.

Abstract: A semiconductor memory includes a first selection transistor and a second selection transistor on one end of a memory string. The first selection transistor includes a channel region in a semiconductor substrate, a channel region in a semiconductor pillar, and a gate electrode connected to a first line. The second selection transistor includes a channel region in the semiconductor pillar and a gate electrode connected to a second line. The first line is connected to a first voltage circuit, and the second line is connected to a second voltage circuit.

Abstract: A semiconductor memory device includes adjacent first and second blocks of memory cells, wherein all the memory cells in each block are erased collectively and each of the blocks includes a plurality of stacks of memory cells above a semiconductor substrate, a dummy cell region including a plurality of stacks of dummy cells above the semiconductor substrate, a source line contact electrically connected to an upper wiring layer and through which a voltage is applied to a source line of the memory cells, and a substrate contact electrically connected to the upper wiring layer and through which a voltage is applied to the semiconductor substrate. The source line contact is disposed between the first and second blocks, and the substrate contact is separated from any of the stacks of memory cells by at least one stack of dummy cells.

Abstract: A nonvolatile semiconductor memory device includes a plurality of memory cells, a plurality of bit lines, each coupled to one of the memory cells, and a control circuit that performs a control for reading data from the first, second, and third memory cells such that when one of the first, second, and third memory cells is selected for reading, the other memory cells are not selected for reading.

Abstract: A non-volatile semiconductor device includes a memory array including a plurality of memory cell transistors electrically connected between bit lines and source lines, wherein the memory array is partitioned into a plurality of memory blocks, and a source line driver configured to set a voltage level of the source lines to a reference voltage level. First and second wirings are respectively connected to a first monitoring position of the source lines and a second monitoring position of the source lines different from the first monitoring position. A selection circuit selects between the first and second monitoring positions. A source line voltage control circuit compares a source line voltage at a selected monitoring position, and outputs a result to the source line driver.

Abstract: A non-volatile semiconductor device includes a memory array including a plurality of memory cell transistors electrically connected between bit lines and source lines, wherein the memory array is partitioned into a plurality of memory blocks, and a source line driver configured to set a voltage level of the source lines to a reference voltage level. First and second wirings are respectively connected to a first monitoring position of the source lines and a second monitoring position of the source lines different from the first monitoring position. A selection circuit selects between the first and second monitoring positions. A source line voltage control circuit compares a source line voltage at a selected monitoring position, and outputs a result to the source line driver.

Abstract: A limiter circuit compares a voltage of a control gate line and a set voltage, thereby switching the logic of a flag signal. A booster circuit starts or stops its operation according to the logic of the flag signal. A leak reference circuit has a function of leaking a leak reference current from the control gate line. A counter generates a first count value by counting the number of times the flag signal logic changes in a condition that a word-line transfer transistor is rendered non-conductive and a leak reference circuit is driven, while the counter generates a second count value by counting the number of times the flag signal logic changes in a condition that the word-line transfer transistor is rendered conductive and the leak reference circuit is undriven. A comparator compares the first count value and the second count value.

Abstract: A developing apparatus and an image forming apparatus including the developing apparatus, the developing apparatus including a developing roller, a mixing transfer unit including a first mixing transfer unit and a second mixing transfer unit, and an auxiliary mixing transfer unit disposed on a transfer path from the first mixing transfer unit to the second mixing transfer unit and to mix the developer transferred by the first mixing transfer unit and the supply toner, wherein the auxiliary mixing transfer unit includes a vertical transfer unit to vertically upward transfer the developer transferred by the first mixing transfer unit and a mixing unit to mix the developer transferred by the first mixing transfer unit and the supply toner injected from an upper side thereof and to connect the second mixing transfer unit to a through hole formed in a lower portion thereof.

Abstract: A memory includes word lines, bit lines, memory cells each having a gate connected to one of the word lines, a word line driver configured to drive voltages of the word lines, and a sense amplifier configured to detect data of the memory cells via the bit lines. The memory cells are connected in series between the bit lines and a source to constitute cell string. The word line driver increases a verification voltage of any of non-selected word lines connected to non-selected memory cells in the cell string at a time of a verify operation in a certain writing loop of a writing stage. The writing stage includes a plurality of writing loops. The writing loops respectively includes a write operation to write data in a selected memory cell in the cell string and a verify operation to verify that the data are written in the selected memory cell.

Abstract: A vacuum pump includes: a rotor that is rotated to perform evacuation; a pump disassembly detection circuit that detects a disassembled state in which the vacuum pump is disassembled; and a pump operation prohibition circuit that prohibits rotary drive of the rotor when the pump operation prohibition circuit determines that the pump disassembly detection circuit has detected the disassembled state.

Abstract: A limiter circuit compares a voltage of a control gate line and a set voltage, thereby switching the logic of a flag signal. A booster circuit starts or stops its operation according to the logic of the flag signal. A leak reference circuit has a function of leaking a leak reference current from the control gate line. A counter generates a first count value by counting the number of times the flag signal logic changes in a condition that a word-line transfer transistor is rendered non-conductive and a leak reference circuit is driven, while the counter generates a second count value by counting the number of times the flag signal logic changes in a condition that the word-line transfer transistor is rendered conductive and the leak reference circuit is undriven. A comparator compares the first count value and the second count value.

Abstract: According to one embodiment, a NAND type flash memory includes a first transfer transistor disposed between first and second memory planes, the first potential transfer terminal of the first transfer transistor being commonly connected to a first word line in the first NAND block and a second word line in the third NAND block, a second transfer transistor disposed at a first end of the first memory plane, the first potential transfer terminal of the second transfer transistor being connected to a third word line in the second NAND block, and a third transfer transistor disposed at a second end of the second memory plane, the first potential transfer terminal of the third transfer transistor being connected to a fourth word line in the fourth NAND block.

Abstract: A memory includes word lines, bit lines, memory cells each having a gate connected to one of the word lines, a word line driver configured to drive voltages of the word lines, and a sense amplifier configured to detect data of the memory cells via the bit lines. The memory cells are connected in series between the bit lines and a source to constitute cell string. The word line driver increases a verification voltage of any of non-selected word lines connected to non-selected memory cells in the cell string at a time of a verify operation in a certain writing loop of a writing stage. The writing stage includes a plurality of writing loops. The writing loops respectively includes a write operation to write data in a selected memory cell in the cell string and a verify operation to verify that the data are written in the selected memory cell.

Abstract: A nonvolatile semiconductor memory of an aspect of the present invention comprises a voltage step-down circuit including a first and a second circuit to achieve a voltage drop and configured to decrease the first voltage to a second voltage less than the first voltage, a transfer transistor to transfer the second voltage to a word line, and a control circuit to generate the second voltage as a first write voltage in a first mode wherein the first write voltage less than or equal to a prescribed magnitude is applied to the word line, and to generate the second voltage as a second write voltage in a second mode wherein the second write voltage greater than the prescribed magnitude is applied to the word line, wherein the difference between the first voltage and the second voltage is greater than or equal to the threshold voltage of the transfer transistor.

Abstract: A developing apparatus and an image forming apparatus including the developing apparatus, the developing apparatus including a developing roller, a mixing transfer unit including a first mixing transfer unit and a second mixing transfer unit, and an auxiliary mixing transfer unit disposed on a transfer path from the first mixing transfer unit to the second mixing transfer unit and to mix the developer transferred by the first mixing transfer unit and the supply toner, wherein the auxiliary mixing transfer unit includes a vertical transfer unit to vertically upward transfer the developer transferred by the first mixing transfer unit and a mixing unit to mix the developer transferred by the first mixing transfer unit and the supply toner injected from an upper side thereof and to connect the second mixing transfer unit to a through hole formed in a lower portion thereof.

Abstract: A memory includes first selective transistors connected between one end of cell strings and bit lines; second selective transistors connected between the other end of the cell strings and a cell source line; a dummy cell string; a first dummy selective transistor connected between one end of the dummy cell string and a dummy bit line and whose gate is connected to a first selective gate line; a second dummy selective transistor connected between the other end of the dummy cell string and the cell source line and whose gate is connected to a second selective gate line, wherein at a time of writing in a selected memory cell, a voltage of a first dummy bit line selected is driven to a different voltage from a voltage of an unselected bit line, and any of the dummy cell transistors connected to the first dummy bit line is written.

Abstract: According to one embodiment, a NAND type flash memory includes a first transfer transistor disposed between first and second memory planes, the first potential transfer terminal of the first transfer transistor being commonly connected to a first word line in the first NAND block and a second word line in the third NAND block, a second transfer transistor disposed at a first end of the first memory plane, the first potential transfer terminal of the second transfer transistor being connected to a third word line in the second NAND block, and a third transfer transistor disposed at a second end of the second memory plane, the first potential transfer terminal of the third transfer transistor being connected to a fourth word line in the fourth NAND block.

Abstract: A memory includes a binary-code setter BCS and the thermometer-code setter TCS, the BCS includes resistance elements with resistance values of R×2N (N=integer) where a reference resistance is indicated by R with the Ns being different from each other; and transistors corresponding to the respective resistance elements, the transistors being controlled by a binary code, and the BCS has a structure obtained by connecting in parallel first structures each constituted by serially connecting a resistance element and the corresponding transistor, and the TCS includes resistance bodies each obtained by connecting in parallel resistance elements with a resistance substantially equal to any of the resistance elements in the BCS; and transistors corresponding to the resistance bodies, controlled by a thermometer code, and the TCS has a structure obtained by connecting in parallel second structures each constituted by serially connecting one of the resistance bodies and the corresponding transistor.