Patents by Inventor Toshifumi Minami
Toshifumi Minami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110163774Abstract: In one embodiment, a probe card includes a substrate, a probe provided on the substrate, and a contact terminal. The contact terminal is provided at a position on the substrate where the contact terminal comes in contact with the probe when a shape anomaly is generated in the probe.Type: ApplicationFiled: June 21, 2010Publication date: July 7, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Toshifumi MINAMI, Hiroki Murotani
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Patent number: 7830715Abstract: A semiconductor device includes a semiconductor substrate including an element region which is surrounded by an element isolation insulation layer, a transistor including a gate electrode which is provided on the element region, and a source region and a drain region which are provided in the first element region, a first auxiliary wiring layer and a second auxiliary wiring layer which extend in a channel length direction and are provided on the element isolation insulation layer such that the first transistor is interposed between the first auxiliary wiring layer and the second auxiliary wiring layer, and a control circuit which sets, while the first transistor is in an ON state, the first auxiliary wiring layer and the second auxiliary wiring layer at a first voltage of the same polarity as a gate voltage of the first transistor that is in the ON state.Type: GrantFiled: June 3, 2008Date of Patent: November 9, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhiro Taniwaki, Toshifumi Minami
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Publication number: 20100237438Abstract: A semiconductor device has a circuit element region formed on a semiconductor substrate, and a protective pattern formed so as to surround the circuit element region.Type: ApplicationFiled: February 16, 2010Publication date: September 23, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Takafumi IKEDA, Takahito Nakazawa, Hideaki Maekawa, Yuuichi Tatsumi, Toshifumi Minami
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Patent number: 7709906Abstract: A semiconductor device includes a gate insulation film provided on a semiconductor substrate, a gate electrode provided on the gate insulation film, a pair of first diffusion layers, a pair of second diffusion layers which are provided in the semiconductor substrate in such a manner that the gate electrode is interposed between the second diffusion layers, the second diffusion layers have a lower impurity concentration than the first diffusion layers, contact wiring lines provided on the first diffusion layers, respectively, and a first insulation layer which is an insulation layer formed in at least one of the second diffusion layers between the gate electrode and the contact wiring lines, the first insulation layer having a greater depth in the semiconductor substrate than the first diffusion layer and a less depth than the second diffusion layer.Type: GrantFiled: November 30, 2007Date of Patent: May 4, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Teppei Higashitsuji, Toshifumi Minami
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Publication number: 20090236672Abstract: A semiconductor device includes a plurality of metal-insulator-semiconductor (MIS) transistors formed on a surface portion of a semiconductor substrate; and an isolation region isolating each of element regions of the MIS transistors, the isolation region including a first isolation region formed with a coating type insulating film embedded in a first trench, the first trench surrounding each of the element regions of the MIS transistors, and a second isolation region formed with a coating type insulating film embedded in a second trench, the second trench surrounding at least one of the first isolation regions with a predetermined distance from each of the first isolation regions, wherein the semiconductor substrate exists between the first isolation region and the second isolation region.Type: ApplicationFiled: February 12, 2009Publication date: September 24, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Hiromitsu HARASHIMA, Toshifumi Minami
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Patent number: 7576411Abstract: In manufacturing a semiconductor memory, a gate oxide film, a polysilicon film and a WSi film are laminated on the major surface of a semiconductor wafer corresponding to both an element region on which a semiconductor chip is to be formed and a dicing region serving as a dicing line. These laminated films are patterned to form a projected dummy pattern having substantially the same wiring structure as that of a gate electrode portion of a selective transistor. The dummy pattern is formed between element isolation regions along a dicing direction at the same time when the gate electrode portion is formed. The dummy pattern prevents stress caused by dicing from being concentrated on an insulation film in the dicing region, thereby minimizing a crack waste. Consequently, in the semiconductor memory, a malfunction due to a large crack waste caused by the dicing, can be avoided.Type: GrantFiled: October 26, 2006Date of Patent: August 18, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Miki Sasaki, Toshifumi Minami
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Publication number: 20090194841Abstract: A semiconductor device has a semiconductor substrate of a first conductivity type; first to third high-voltage insulated-gate field effect transistors formed on a principal surface of the semiconductor substrate; a first device isolation insulating film that is formed in the semiconductor substrate and isolates the first high-voltage insulated-gate field effect transistor and the second high-voltage insulated-gate field effect transistor from each other; a second device isolation insulating film that is formed in the semiconductor substrate and isolates the first high-voltage insulated-gate field effect transistor and the third high-voltage insulated-gate field effect transistor from each other; a first impurity diffusion layer of the first conductivity type that is formed below the first device isolation insulating film; and a second impurity diffusion layer of the first conductivity type that is formed below the second device isolation insulating film.Type: ApplicationFiled: January 28, 2009Publication date: August 6, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Norio MAGOME, Toshifumi Minami, Tomoaki Hatano, Norihisa Arai
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Publication number: 20090039408Abstract: A nonvolatile semiconductor memory of an aspect of the present invention comprises a first element isolation insulating film containing an organic substance which surrounds a first region, a memory cell arranged in the first region, a second element isolation insulating film containing an organic substance which surrounds a second region, a peripheral transistor arranged in the second region, and a first impurity layer which is provided in the semiconductor substrate along a side surface of the second element isolation insulating film.Type: ApplicationFiled: August 7, 2008Publication date: February 12, 2009Inventors: Tomoaki Hatano, Toshifumi Minami, Norihisa Arai
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Publication number: 20080298125Abstract: A semiconductor device includes a semiconductor substrate including an element region which is surrounded by an element isolation insulation layer, a transistor including a gate electrode which is provided on the element region, and a source region and a drain region which are provided in the first element region, a first auxiliary wiring layer and a second auxiliary wiring layer which extend in a channel length direction and are provided on the element isolation insulation layer such that the first transistor is interposed between the first auxiliary wiring layer and the second auxiliary wiring layer, and a control circuit which sets, while the first transistor is in an ON state, the first auxiliary wiring layer and the second auxiliary wiring layer at a first voltage of the same polarity as a gate voltage of the first transistor that is in the ON state.Type: ApplicationFiled: June 3, 2008Publication date: December 4, 2008Inventors: Kazuhiro TANIWAKI, Toshifumi MINAMI
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Patent number: 7402904Abstract: A semiconductor device includes a first wiring layer having a first wiring pitch and a second wiring layer having a second wiring pitch that differs from the first wiring pitch. The device further includes a third wiring layer which connects the first wiring layer and the second wiring layer and has a wiring incident angle of less than 45 degrees to at least the first wiring layer.Type: GrantFiled: March 22, 2005Date of Patent: July 22, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Toshifumi Minami, Satoshi Oonuki
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Publication number: 20080128795Abstract: A semiconductor device includes a gate insulation film provided on a semiconductor substrate, a gate electrode provided on the gate insulation film, a pair of first diffusion layers, a pair of second diffusion layers which are provided in the semiconductor substrate in such a manner that the gate electrode is interposed between the second diffusion layers, the second diffusion layers have a lower impurity concentration than the first diffusion layers, contact wiring lines provided on the first diffusion layers, respectively, and a first insulation layer which is an insulation layer formed in at least one of the second diffusion layers between the gate electrode and the contact wiring lines, the first insulation layer having a greater depth in the semiconductor substrate than the first diffusion layer and a less depth than the second diffusion layer.Type: ApplicationFiled: November 30, 2007Publication date: June 5, 2008Inventors: Teppei Higashitsuji, Toshifumi Minami
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Publication number: 20070040242Abstract: In manufacturing a semiconductor memory, a gate oxide film, a polysilicon film and a WSi film are laminated on the major surface of a semiconductor wafer corresponding to both an element region on which a semiconductor chip is to be formed and a dicing region serving as a dicing line. These laminated films are patterned to form a projected dummy pattern having substantially the same wiring structure as that of a gate electrode portion of a selective transistor. The dummy pattern is formed between element isolation regions along a dicing direction at the same time when the gate electrode portion is formed. The dummy pattern prevents stress caused by dicing from being concentrated on an insulation film in the dicing region, thereby minimizing a crack waste. Consequently, in the semiconductor memory, a malfunction due to a large crack waste caused by the dicing, can be avoided.Type: ApplicationFiled: October 26, 2006Publication date: February 22, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Miki SASAKI, Toshifumi MINAMI
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Patent number: 7176061Abstract: In manufacturing a semiconductor memory, a gate oxide film, a polysilicon film and a WSi film are laminated on the major surface of a semiconductor wafer corresponding to both an element region on which a semiconductor chip is to be formed and a dicing region serving as a dicing line. These laminated films are patterned to form a projected dummy pattern having substantially the same wiring structure as that of a gate electrode portion of a selective transistor. The dummy pattern is formed between element isolation regions along a dicing direction at the same time when the gate electrode portion is formed. The dummy pattern prevents stress caused by dicing from being concentrated on an insulation film in the dicing region, thereby minimizing a crack waste. Consequently, in the semiconductor memory, a malfunction due to a large crack waste caused by the dicing, can be avoided.Type: GrantFiled: March 1, 2005Date of Patent: February 13, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Miki Sasaki, Toshifumi Minami
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Patent number: 7143476Abstract: In order to provide a tilt hinge small in size and diameter capable of generating a stable friction torque of approximately 100 kgf/mm, a hinge friction-rotatably coupling a first member and a second member that are relatively opened/closed includes: a holder attached to one of the first member and the second member; a shaft attached to the other one of the first member and the second member to be rotatable relative to the holder and immovable in an axial direction; a plurality of first friction discs restrained by the holder to be rotatable and movable in the axial direction, with the shaft being inserted through insertion holes thereof; a plurality of second friction discs interposed between the first friction discs to be movable in the axial direction with rotation thereof restrained by the shaft; and a plurality of disc springs and/or spring washers attached to the shaft so as to bring the first friction discs and the second friction discs to be in contact with each other by pressing the first friction diType: GrantFiled: September 24, 2004Date of Patent: December 5, 2006Assignee: Katoh Electrical Machinery Co., Ltd.Inventor: Toshifumi Minami
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Publication number: 20060038292Abstract: A semiconductor device includes a first wiring layer having a first wiring pitch and a second wiring layer having a second wiring pitch that differs from the first wiring pitch. The device further includes a third wiring layer which connects the first wiring layer and the second wiring layer and has a wiring incident angle of less than 45 degrees to at least the first wiring layer.Type: ApplicationFiled: March 22, 2005Publication date: February 23, 2006Inventors: Toshifumi Minami, Satoshi Oonuki
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Publication number: 20060032022Abstract: The present invention provides a tilt hinge configured so that friction torque members accommodated in a leaf spring housing can be visually checked from outside and an electronic apparatus using the tilt hinge. The tilt hinge pivotally couples a first member to a second member and includes: a holder attached to one of the first and second members and including a leaf spring housing; a shaft attached to the other of the first and second members and rotatably supported by the leaf spring housing; and a plurality of friction torque members accommodated in the leaf spring housing and generating a friction torque when the holder or the shaft rotates. The friction torque members include a friction torque member that is constrained from rotation by the holder and a friction torque member that is constrained from rotation by the shaft.Type: ApplicationFiled: July 26, 2005Publication date: February 16, 2006Inventor: Toshifumi Minami
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Publication number: 20050145993Abstract: In manufacturing a semiconductor memory, a gate oxide film, a polysilicon film and a WSi film are laminated on the major surface of a semiconductor wafer corresponding to both an element region on which a semiconductor chip is to be formed and a dicing region serving as a dicing line. These laminated films are patterned to form a projected dummy pattern having substantially the same wiring structure as that of a gate electrode portion of a selective transistor. The dummy pattern is formed between element isolation regions along a dicing direction at the same time when the gate electrode portion is formed. The dummy pattern prevents stress caused by dicing from being concentrated on an insulation film in the dicing region, thereby minimizing a crack waste. Consequently, in the semiconductor memory, a malfunction due to a large crack waste caused by the dicing, can be avoided.Type: ApplicationFiled: March 1, 2005Publication date: July 7, 2005Inventors: Miki Sasaki, Toshifumi Minami
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Patent number: 6879025Abstract: A semiconductor device includes a dicing region provided on a semiconductor substrate to separate a plurality of semiconductor chips each having a gate portion from each other. The semiconductor device further includes a plurality of element isolation regions provided on a surface portion of the semiconductor substrate within the dicing region, a plurality of first dummy patterns formed on a surface of the semiconductor substrate so as to correspond to intervals of the plurality of element isolation regions, respectively, and a plurality of second dummy patterns formed above the semiconductor substrate within the dicing region so as to correspond to the plurality of first dummy patterns, respectively.Type: GrantFiled: December 5, 2001Date of Patent: April 12, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Miki Sasaki, Toshifumi Minami
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Publication number: 20050066475Abstract: In order to provide a tilt hinge small in size and diameter capable of generating a stable friction torque of approximately 100 kgf/mm, a hinge friction-rotatably coupling a first member and a second member that are relatively opened/closed includes: a holder attached to one of the first member and the second member; a shaft attached to the other one of the first member and the second member to be rotatable relative to the holder and immovable in an axial direction; a plurality of first friction discs restrained by the holder to be rotatable and movable in the axial direction, with the shaft being inserted through insertion holes thereof; a plurality of second friction discs interposed between the first friction discs to be movable in the axial direction with rotation thereof restrained by the shaft; and a plurality of disc springs and/or spring washers attached to the shaft so as to bring the first friction discs and the second friction discs to be in contact with each other by pressing the first friction diType: ApplicationFiled: September 24, 2004Publication date: March 31, 2005Inventor: Toshifumi Minami
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Patent number: 6713837Abstract: A semiconductor device has a first conductor, a first insulating film formed on the first conductor, a columnar second conductor formed on the first conductor, and a third conductor formed on a top surface of the second columnar conductor and first insulating film. A second insulating film is formed on the third conductor and the first insulating film. The second insulating film is thinned above the second conductor. The second and third conductors form a fuse that is blown if irradiated with a laser beam. The fuse needs a small space, and a peripheral circuit related to the fuse is formed on one side of the fuse.Type: GrantFiled: March 10, 2000Date of Patent: March 30, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Sadayuki Mori, Toshifumi Minami