Patents by Inventor Toshifumi Minami

Toshifumi Minami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020043700
    Abstract: In manufacturing a semiconductor memory, a gate oxide film, a polysilicon film and a WSi film are laminated on the major surface of a semiconductor wafer corresponding to both an element region on which a semiconductor chip is to be formed and a dicing region serving as a dicing line. These laminated films are patterned to form a projected dummy pattern having substantially the same wiring structure as that of a gate electrode portion of a selective transistor. The dummy pattern is formed between element isolation regions along a dicing direction at the same time when the gate electrode portion is formed. The dummy pattern prevents stress caused by dicing from being concentrated on an insulation film in the dicing region, thereby minimizing a crack waste. Consequently, in the semiconductor memory, a malfunction due to a large crack waste caused by the dicing, can be avoided.
    Type: Application
    Filed: December 5, 2001
    Publication date: April 18, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Miki Sasaki, Toshifumi Minami
  • Patent number: 6355967
    Abstract: In the fuse element structure of the semiconductor device, the first insulating film region is provided in a groove-like manner in the semiconductor substrate. Further, the fuse element is formed on the first insulating film region, and the second insulating film region is formed on the region on the fuse element and the first insulating film. The metal plug is connected to the fuse element, and the surface thereof is exposed to the surface of the second insulating film region. With this structure, the meltdown of the fuse by the laser blow is facilitated, and the area of the fuse is reduced. Thus, as the downsizing of the element is further advanced, it is possible to provide a fuse element structure capable of melting down a fuse without causing an affect on another fuse adjacent to the melted-down fuse with the scattering pieces thereof.
    Type: Grant
    Filed: April 20, 2000
    Date of Patent: March 12, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshifumi Minami
  • Publication number: 20020000638
    Abstract: In the fuse element structure of the semiconductor device, the first insulating film region is provided in a groove-like manner in the semiconductor substrate. Further, the fuse element is formed on the first insulating film region, and the second insulating film region is formed on the region on the fuse element and the first insulating film. The metal plug is connected to the fuse element, and the surface thereof is exposed to the surface of the second insulating film region. With this structure, the meltdown of the fuse by the laser blow is facilitated, and the area of the fuse is reduced. Thus, as the downsizing of the element is further advanced, it is possible to provide a fuse element structure capable of melting down a fuse without causing an affect on another fuse adjacent to the melted-down fuse with the scattering pieces thereof.
    Type: Application
    Filed: April 20, 2000
    Publication date: January 3, 2002
    Inventor: Toshifumi Minami