Abstract: A data latch circuit according to embodiments described herein includes a first circuit and a second circuit. The first circuit has a first transistor with a first conductivity type and a second transistor with a second conductivity type that differs from the first conductivity type being connected in series and stores a first logical value. The second circuit has a third transistor with the first conductivity type and a fourth transistor with the second conductivity type being connected in series and stores a second logical value being an inversion of the first logical value. The data latch circuit enables one of a first voltage and a second voltage that differs from the first voltage to be applied to back gates of the first transistor and the third transistor and enables a third voltage to be applied to sources of the first transistor and the third transistor.

Abstract: Desired is development of novel CDN derivatives having STING agonist activity; and a therapeutic agents and/or therapeutic methods using the novel CDN derivatives for diseases associated with STING agonist activity. Further desired is development of a therapeutic agents and/or therapeutic methods capable of delivering the novel CDN derivatives specifically to targeted cells and organs for diseases associated with STING agonist activity. The present invention provides novel CDN derivatives having potent STING agonist activity, and antibody-CDN derivative conjugates including the novel CDN derivatives.

Abstract: A polishing apparatus that can improve an accuracy of position coordinates associated with a measured value of film thickness is disclosed. The polishing apparatus includes: a pad-thickness measuring device configured to measure a thickness of the polishing pad; an optical film-thickness measuring device configured to emit light obliquely to the substrate, and determine measured values of film thickness at measurement points; and a controller configured to associates the measured values of the film thickness with measurement coordinates indicating positions of the measurement points.

Abstract: A semiconductor device includes a first pad, a second pad, a first output driver provided for the first pad and configured to output a first transmission signal to the first pad, a second output driver provided for the second pad and configured to output a second transmission signal to the second pad, a register that stores first and second calibration values, a first reference resistor for the first pad and having a resistance value that is set according to the first calibration value, a second reference resistor for the second pad and having a resistance value that is set according to the second calibration value, a first setting circuit configured to calibrate a resistance value of the first output driver using the first reference resistor, and a second setting circuit configured to calibrate a resistance value of the second output driver using the second reference resistor.

Abstract: A semiconductor device includes a first pad, a second pad, a first output driver provided for the first pad and configured to output a first transmission signal to the first pad, a second output driver provided for the second pad and configured to output a second transmission signal to the second pad, a register that stores first and second calibration values, a first reference resistor for the first pad and having a resistance value that is set according to the first calibration value, a second reference resistor for the second pad and having a resistance value that is set according to the second calibration value, a first setting circuit configured to calibrate a resistance value of the first output driver using the first reference resistor, and a second setting circuit configured to calibrate a resistance value of the second output driver using the second reference resistor.

Abstract: There is provided a gas solution supply apparatus capable of preventing bubbles from being generated in use at a point-of-use even if gas solution to be provided to a point-of-use has a high concentration. The gas solution supply apparatus 1 includes: a gas dissolving unit 4 that dissolves a source gas in a source liquid to produce a first gas solution; a first gas-liquid separator 10 that stores the first gas solution produced and produces a second gas solution through gas-liquid separation of the first gas solution; a pressure reducer 17 that depressurizes the second gas solution produced in the first gas-liquid separator 10; and a second gas-liquid separator 12 that stores the depressurized second gas solution and produces a third gas solution through gas-liquid separation of the second gas solution. The third gas solution is supplied to a point-of-use.

Abstract: A semiconductor memory device includes an output pin configured for connection with a memory controller, an output circuit configured to output through the output pin a voltage signal that changes over time in accordance with one or more bits of data to be output to the memory controller, and a control circuit configured to temporarily change a drive capability of the output circuit each time a voltage signal corresponding to one bit of the data is output through the output pin.

Abstract: A semiconductor memory includes a memory cell, a bit line electrically connected to the memory cell, a sense amplifier including a first latch circuit, a first hookup circuit, a second latch circuit, a first wiring, and a first pre-charge circuit. The sense amplifier is in a first circuit area. The first hookup circuit is in a second circuit area and configured to control connection between the bit line and the sense amplifier. The first wiring is connected between the first latch circuit and the second latch circuit. The first pre-charge circuit includes a first transistor in a third circuit area between the first circuit area and the second circuit area. The first transistor has a first end connected to the first wiring at a first position in the third circuit area and a second end connectable to a terminal supplied with one of a pre-charge voltage and a ground voltage.

Abstract: A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.

Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.

Abstract: A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells, a word line connected to the plurality of memory cells, a plurality of bit lines connected respectively to the plurality of memory cells, a sense amplifier connected to the plurality of bit lines, and a controller configured to execute a write operation in a plurality of program loops each including a program operation and a verify operation. The sense amplifier is configured to apply a first voltage, a second voltage higher than the first voltage, a third voltage higher than the second voltage, and a fourth voltage higher than the third voltage to first, second, third, and fourth bit lines of the plurality of bit lines, respectively, while a program voltage is applied to the word line in the program operation.

Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells, a word line connected to the plurality of memory cells, a plurality of bit lines connected respectively to the plurality of memory cells, a sense amplifier connected to the plurality of bit lines, and a controller configured to execute a write operation in a plurality of program loops each including a program operation and a verify operation. The sense amplifier is configured to apply a first voltage, a second voltage higher than the first voltage, a third voltage higher than the second voltage, and a fourth voltage higher than the third voltage to first, second, third, and fourth bit lines of the plurality of bit lines, respectively, while a program voltage is applied to the word line in the program operation.

Abstract: A gas solution manufacturing device 1 includes a gas supply line 2 configured to supply a gas as a raw material of a gas solution, a liquid supply line 3 configured to supply a liquid as a raw material of the gas solution, a gas solution production unit 4 configured to mix the gas and the liquid together to produce the gas solution, a gas-liquid separation unit 5 configured to perform gas-liquid separation of the produced gas solution into a supplied liquid to be supplied to a use point and a discharged gas to be discharged through an exhaust port, and a gas dissolving unit 6 provided in the liquid supply line 4 and configured to dissolve the discharged gas resulting from the gas-liquid separation in the liquid. The gas dissolving unit 6 is configured with a hollow fiber membrane configured with a gas permeable membrane.

Abstract: A gas dissolved liquid manufacturing device includes: a pump configured to pressurize a liquid; a pipe communicating with the pump; a nozzle disposed in the pipe, the nozzle being configured to generate micro bubbles using a supplied gas; and a gas-liquid separation tank whose upper part communicates with the pipe, the gas-liquid separation tank being configured to separate a gas-liquid mixture generated by the nozzle into a gas and a liquid.

Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.

Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation, and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.

Abstract: A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.

Abstract: A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.