Abstract: Methods for manufacturing semiconductor light-emitting devices and semiconductor light-emitting devices having a high radiating performance and can include a metallic laminate substrate, a semiconductor light-emitting chip and a transparent resin. The metallic laminate substrate can include a cavity so as to be able to accurately mount the light-emitting chip, and also can structures to efficiently radiate heat generated from the light-emitting chip. The transparent resin to encapsulate the semiconductor light-emitting chip in the cavity can include various wavelength converting materials. Additionally, the light-emitting devices can be manufactured in manufacturing processes similar to conventional light-emitting devices.

Abstract: An image forming apparatus includes: an image carrier that carries and transports a latent image; a charging member that is arranged to be in contact with a surface of the image carrier; a developing device that supplies toner to the image carrier and forms a toner image; a density detection unit that detects a density of the toner image; a pattern detection unit that detects a predetermined density variation pattern based on a detection result of the density detection unit according to the toner image; and a determination unit that determines a state of the charging member based on the number of the predetermined density variation patterns detected within a predetermined period of time.

Abstract: According to one embodiment, a semiconductor memory device includes a first transistor which includes a first end coupled to a first node, a second end, and a gate coupled to the second end. A second transistor includes a third end coupled to the first node, a fourth end, and a gate coupled to the fourth end. A third transistor is provided between a first bit line and a second node in a first sense amplifier. A selector is configured to supply a gate of the third transistor with one of a potential of the second end and a potential of the fourth end.

Abstract: An apparatus and method of polishing a substrate is described. The polishing includes: rotating a substrate; pressing a first polishing tool against an edge portion of the substrate to polish the edge portion; and pressing a second polishing tool against the edge portion of the substrate to polish the edge portion. The second polishing tool is located more inwardly than the first polishing tool with respect to a radial direction of the substrate. The first polishing tool has a polishing surface rougher than a polishing surface of the second polishing tool.

Abstract: Methods for manufacturing semiconductor light-emitting devices and semiconductor light-emitting devices having a high radiating performance and can include a metallic laminate substrate, a semiconductor light-emitting chip and a transparent resin. The metallic laminate substrate can include a cavity so as to be able to accurately mount the light-emitting chip, and also can structures to efficiently radiate heat generated from the light-emitting chip. The transparent resin to encapsulate the semiconductor light-emitting chip in the cavity can include various wavelength converting materials. Additionally, the light-emitting devices can be manufactured in manufacturing processes similar to conventional light-emitting devices.

Abstract: An apparatus and method of polishing a substrate is described. The polishing includes: rotating a substrate; pressing a first polishing tool against an edge portion of the substrate to polish the edge portion; and pressing a second polishing tool against the edge portion of the substrate to polish the edge portion. The second polishing tool is located more inwardly than the first polishing tool with respect to a radial direction of the substrate. The first polishing tool has a polishing surface rougher than a polishing surface of the second polishing tool.

Abstract: An apparatus and method of polishing a substrate is described. The polishing includes: rotating a substrate; pressing a first polishing tool against an edge portion of the substrate to polish the edge portion; and pressing a second polishing tool against the edge portion of the substrate to polish the edge portion. The second polishing tool is located more inwardly than the first polishing tool with respect to a radial direction of the substrate. The first polishing tool has a polishing surface rougher than a polishing surface of the second polishing tool.

Abstract: An apparatus and method of polishing a substrate is described. The polishing includes: rotating a substrate; pressing a first polishing tool against an edge portion of the substrate to polish the edge portion; and pressing a second polishing tool against the edge portion of the substrate to polish the edge portion. The second polishing tool is located more inwardly than the first polishing tool with respect to a radial direction of the substrate. The first polishing tool has a polishing surface rougher than a polishing surface of the second polishing tool.

Abstract: According to one embodiment, an interface includes first to third input circuits, delay and selection circuits. The first input circuit outputs an active first internal signal in response to an active first control signal received by a memory device. The second input circuit outputs an active second internal signal in response to an active second control signal received by the device while the device is receiving the active first control signal. The delay circuit outputs a selection signal in first or second states after the elapse of a first period from inactivation or activation of the first control signal. The selection circuit outputs the first and second internal signals as an enable signal while receiving the selection signal of the first and second states. The third input circuit outputs an input signal received from the outside from the interface to inside the device while receiving the active enable signal.

Abstract: A semiconductor memory according to one embodiment includes: a memory cell array including a plurality of memory cells storing data, a first buffer circuit for inputting/outputting data to and from the first memory cell array, a data transfer circuit connected with the first buffer circuit via the first data bus and configured to control data transfer, and a control circuit configured to control a first mode and a second mode. The data transfer circuit performs control such that a bus width of the first data bus differs between the first mode and the second mode.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory, a second memory and a control circuit. The first memory includes a first bank number. The second memory includes a second bank number larger than the first bank number. The control circuit controls a precharge operation with respect to bit lines provided in the first and second memories. When performing, with respect to the first memory, a synchronous operation that is effected in synchronization with a clock, the control circuit changes over a second precharge operation to an operation time different from a first precharge operation during a period from the end of the initial first precharge operation to the start of the subsequent second precharge operation after receiving an address.

Abstract: According to one embodiment, an interface includes first to third input circuits, delay and selection circuits. The first input circuit outputs an active first internal signal in response to an active first control signal received by a memory device. The second input circuit outputs an active second internal signal in response to an active second control signal received by the device while the device is receiving the active first control signal. The delay circuit outputs a selection signal in first or second states after the elapse of a first period from inactivation or activation of the first control signal. The selection circuit outputs the first and second internal signals as an enable signal while receiving the selection signal of the first and second states. The third input circuit outputs an input signal received from the outside from the interface to inside the device while receiving the active enable signal.

Abstract: According to one embodiment, a semiconductor memory device includes a memory array, an address counter, an address detecting circuit and a control circuit. The memory array has a plurality of memory cells arranged at crossing positions of word lines and bit lines. The address counter increments an address including a row address and a column address in synchronism with a clock to sequentially output the incremented addresses. The address detecting circuit detects an address previous to an address including a row address to which the row address is switched at the address output from the address counter to output a detection signal. The control circuit performs a precharging operation to the bit lines connected to the memory cells according to the detection signal output from the address detecting circuit.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory and a second memory, a data path between the first memory and the second memory, a register configured to store first data transferred through the data path in a first direction, and a comparison circuit configured to compare second data transferred through the data path in a second direction with the first data stored in the register so as to detect a fault location.

Abstract: A memory system includes: a plurality of banks each including a memory cell array and a sense amplifier; a buffer circuit electrically connected to the plurality of banks; a switch circuit configured to switch on and off an electrical connection between the buffer circuit and each of the plurality of banks an interface electrically connected to the buffer circuit; and a controller configured to control the plurality of banks, the buffer circuit, the switch circuit and the interface, wherein for reading data held in the memory cell array by outputting the data to the interface in 5 clock cycles, the controller is configured to control the switch circuit in order that the switch circuit electrically connects a selected one of the banks to the buffer circuit upon the lapse of 1.5 clock cycles after a clock is inputted into the selected bank.

Abstract: A semiconductor memory device configured to perform a clock synchronous burst read operation includes a plurality of buffer memories having different bank structures, and first and second data latch circuits storing read data read from the plurality of buffer memories. The semiconductor memory device further includes a control circuit that controls a timing of starting counting up addresses and a timing of storing read data in the first data latch circuit at the time of the clock synchronous burst read operation in accordance with the bank structure of the buffer memory as a read operation target.

Abstract: According to one embodiment, a memory system includes a NAND flash memory, a first unit, and an second unit. Memory cells capable of holding data and management data as a first control signal. Memory cells are arranged in a matrix in the NAND flash memory. The first unit holds a second and a third signal. The second signal is made variable in accordance with an output frequency. The third signal is made variable. The second unit outputs the data to an outside in accordance with the first to third signals. The second unit includes a buffer unit including first to third transistors. The output frequency includes a first frequency and a second frequency. If the first to third transistors output the data to the outside in synchronization with the second frequency, the first to third transistors may be turned on regardless of a value of the first control signal.

Abstract: An image forming apparatus includes a photoreceptor, a discharging device that discharges the photoreceptor, to regard a potential of the photoreceptor as a first potential, a charging device that charges the photoreceptor by proximity discharge, to regard a potential of the photoreceptor as a second potential. The charging device charges the photoreceptor for a plurality of times when changing the potential of the photoreceptor from the first potential to the second potential, and a change amount in potential of the photoreceptor in each charge is substantially the same.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory, a second memory and a control circuit. The first memory includes a first bank number. The second memory includes a second bank number larger than the first bank number. The control circuit controls a precharge operation with respect to bit lines provided in the first and second memories. When performing, with respect to the first memory, a synchronous operation that is effected in synchronization with a clock, the control circuit changes over a second precharge operation to an operation time different from a first precharge operation during a period from the end of the initial first precharge operation to the start of the subsequent second precharge operation after receiving an address.

Abstract: According to one embodiment, a semiconductor memory device includes a memory array, an address counter, an address detecting circuit and a control circuit. The memory array has a plurality of memory cells arranged at crossing positions of word lines and bit lines. The address counter increments an address including a row address and a column address in synchronism with a clock to sequentially output the incremented addresses. The address detecting circuit detects an address previous to an address including a row address to which the row address is switched at the address output from the address counter to output a detection signal. The control circuit performs a precharging operation to the bit lines connected to the memory cells according to the detection signal output from the address detecting circuit.