Patents by Inventor Toshifumi Watanabe
Toshifumi Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210202007Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation, and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.Type: ApplicationFiled: March 15, 2021Publication date: July 1, 2021Applicant: Kioxia CorporationInventors: Akio SUGAHARA, Akihiro IMAMOTO, Toshifumi WATANABE, Mami KAKOI, Kohei MASUDA, Masahiro YOSHIHARA, Naofumi ABIKO
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Patent number: 11024360Abstract: A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.Type: GrantFiled: February 24, 2020Date of Patent: June 1, 2021Assignee: KIOXIA CORPORATIONInventors: Toshifumi Watanabe, Naofumi Abiko
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Publication number: 20210065770Abstract: A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.Type: ApplicationFiled: February 24, 2020Publication date: March 4, 2021Inventors: Toshifumi WATANABE, Naofumi ABIKO
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Patent number: 10907268Abstract: A method for producing a multi-layer bus bar unit includes preparing a plurality of metal flat plate-shaped bus bars, each with electrode terminal parts at two or more locations, depositing a coating film over an entire surface of each bus bar by electrodeposition coating, subjecting a coating film of a predetermined bus bar to a heating treatment so that the coating film is completely cured, subjecting another bus bar to a heat treatment so that the bus bar is semi-cured, and obtaining a multi-layer structure by alternately overlapping, and then subjecting to a pressure and heating treatment, the bus bar with the completely-cured coating film and the bus bar with the semi-cured coating film, so that the semi-cured coating film is completely cured and the plurality of bus bars adhere to each other by the completely-cured coating film.Type: GrantFiled: May 16, 2016Date of Patent: February 2, 2021Assignees: SUNCALL CORPORATION, STANLEY ELECTRIC CO., LTD.Inventors: Masaya Nakagawa, Shojiro Wakabayashi, Mamoru Yuasa, Toshifumi Watanabe
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Publication number: 20210017056Abstract: A gas dissolved liquid manufacturing device includes: a pump configured to pressurize a liquid; a pipe communicating with the pump; a nozzle disposed in the pipe, the nozzle being configured to generate micro bubbles using a supplied gas; and a gas-liquid separation tank whose upper part communicates with the pipe, the gas-liquid separation tank being configured to separate a gas-liquid mixture generated by the nozzle into a gas and a liquid.Type: ApplicationFiled: July 7, 2020Publication date: January 21, 2021Inventors: Yoichi NAKAGAWA, Suguru OZAWA, Yuji ARAKI, Toshifumi WATANABE
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Patent number: 10872673Abstract: A semiconductor memory cell includes a memory cell, a word line and a source line both connected to the memory cell, and a control circuit. During a read operation on the memory cell, the control circuit applies a first voltage to the word line, applies a second voltage greater than the first voltage to the word line, and then applies a third voltage which is greater than the first voltage and smaller than the second voltage to the word line. During the read operation on the memory cell, the control circuit also applies a fourth voltage to the source line according to a timing at which the second voltage is applied to the word line, and then applies a fifth voltage smaller than the fourth voltage to the source line.Type: GrantFiled: August 27, 2019Date of Patent: December 22, 2020Assignee: Toshiba Memory CorporationInventors: Toshifumi Watanabe, Naofumi Abiko, Mario Sako
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Publication number: 20200385295Abstract: A gas dissolution supply apparatus dissolves a gas supplied from a gas supply unit in a liquid supplied from a liquid supply unit to produce a gas dissolution in a gas dissolving unit, stores the gas dissolution produced in the gas dissolving unit in a gas dissolution tank, supplies the gas dissolution from the gas dissolution tank to a point of use, measures the flow rate of a part of the gas dissolution supplied to the point of use that is returned to the gas dissolving unit, and adjusts the flow rate of the liquid supplied from the liquid supply unit to the gas dissolving unit based on the result of the measurement.Type: ApplicationFiled: May 28, 2020Publication date: December 10, 2020Inventors: Suguru OZAWA, Yuji ARAKI, Toshifumi WATANABE, Yoichi NAKAGAWA
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Patent number: 10835876Abstract: A gas-dissolved liquid producing apparatus 1 includes a gas supply unit 2, a first liquid supply unit 3, a gas-dissolved liquid generator 4, a second liquid generator 20, a second liquid supply unit 21, a flow rate measuring unit 14, and a controller 23. The controller 23 controls the supply amount of the first liquid to be supplied to the gas-dissolved liquid generator 4 according to the flow rate of circulated gas-dissolved liquid measured by the flow rate measuring unit 14. The gas-dissolved liquid generator 4 dissolves gas supplied from the gas supply unit 2 in first liquid supplied from the first liquid supply unit 3 and second liquid supplied from the second liquid supply unit 21 to generate gas-dissolved liquid.Type: GrantFiled: December 19, 2018Date of Patent: November 17, 2020Assignee: EBARA CORPORATIONInventors: Yoichi Nakagawa, Suguru Ozawa, Toshifumi Watanabe, Tao Xu
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Patent number: 10811284Abstract: A substrate processing method which can clean a peripheral portion of a substrate after polishing and can check the cleaning effect of the peripheral portion of the substrate is disclosed. The substrate processing method includes polishing a peripheral portion of the substrate by pressing a polishing tape having abrasive grains against the peripheral portion of the substrate with a first head, cleaning the peripheral portion of the substrate by supplying a cleaning liquid to the peripheral portion of the substrate after polishing, bringing a tape having no abrasive grains into contact with the peripheral portion of the substrate after cleaning by a second head, applying light to the tape and receiving reflected light from the tape by a sensor, and judging that the peripheral portion of the substrate is contaminated when an intensity of the received reflected light is lower than a predetermined value.Type: GrantFiled: March 22, 2018Date of Patent: October 20, 2020Assignee: EBARA CORPORATIONInventors: Toshifumi Watanabe, Satoru Yamamoto, Yu Machida
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Patent number: 10734562Abstract: Some embodiments provide a substrate terminal board in which the number of components is reduced by utilizing a conductor board per se constituting the substrate terminal board while ensuring heat dissipation, and which has a simple structure. Heat-dissipation fins can be cut and raised at a plurality of positions around element mounting portions of an upper-substrate conductor board, thus providing heat-dissipation fins and heat-dissipation openings. The upper-substrate conductor board can be coated with a paint film to form an upper substrate. A lower-substrate conductor board can be coated with the paint film to form a lower substrate. In a pressing/heating process, the lower substrate and the upper substrate can overlap each other and be vertically pressed while the lower substrate and the upper substrate are heated to completely cure the paint film, thereby causing the paint film on the lower substrate and the paint film on the upper substrate to adhere to each other.Type: GrantFiled: November 13, 2017Date of Patent: August 4, 2020Assignees: SUNCALL CORPORATION, STANLEY ELECTRIC CO., LTD.Inventors: Masaya Nakagawa, Shojiro Wakabayashi, Mamoru Yuasa, Toshifumi Watanabe
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Publication number: 20200194087Abstract: A semiconductor memory cell includes a memory cell, a word line and a source line both connected to the memory cell, and a control circuit. During a read operation on the memory cell, the control circuit applies a first voltage to the word line, applies a second voltage greater than the first voltage to the word line, and then applies a third voltage which is greater than the first voltage and smaller than the second voltage to the word line. During the read operation on the memory cell, the control circuit also applies a fourth voltage to the source line according to a timing at which the second voltage is applied to the word line, and then applies a fifth voltage smaller than the fourth voltage to the source line.Type: ApplicationFiled: August 27, 2019Publication date: June 18, 2020Inventors: Toshifumi WATANABE, Naofumi ABIKO, Mario SAKO
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Patent number: 10632587Abstract: To provide a polishing apparatus capable of polishing bevel portions of varying shape by selecting a suitable polishing recipe, based on a state before polishing. The polishing apparatus 100 comprises: a holding/polishing unit 102 for holding and polishing a workpiece W1; and an identifying unit 104 for identifying data 104a associated with a state of the peripheral portion of the substrate W1 before polishing. The holding/polishing unit 102 comprises: a holder 106 for holding and rotating the substrate W1; and a polisher 108 for polishing the peripheral portion of the substrate W1 by pressing a polishing member against the peripheral portion. A polishing-condition determiner 110 determines a polishing condition, based on data 104a indicating to which type, of a plurality of shape-related types, the shape of a given peripheral portion belongs.Type: GrantFiled: January 6, 2017Date of Patent: April 28, 2020Assignee: EBARA CORPORATIONInventors: Masayuki Nakanishi, Toshifumi Watanabe, Kenji Kodera
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Patent number: 10580501Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array having a plurality of memory cells, a plurality of bit lines, each bit line being connected to one of the memory cells in the plurality of memory cells, and a word line commonly connected to the plurality of memory cells. A control circuit is configured to apply a program voltage to the word line and to change a voltage applied to a first bit line in the plurality of bit lines within a first period in which the program voltage is being applied to the word line.Type: GrantFiled: August 27, 2018Date of Patent: March 3, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Toshifumi Watanabe, Naofumi Abiko
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Publication number: 20190348131Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array having a plurality of memory cells, a plurality of bit lines, each bit line being connected to one of the memory cells in the plurality of memory cells, and a word line commonly connected to the plurality of memory cells. A control circuit is configured to apply a program voltage to the word line and to change a voltage applied to a first bit line in the plurality of bit lines within a first period in which the program voltage is being applied to the word line.Type: ApplicationFiled: August 27, 2018Publication date: November 14, 2019Inventors: Toshifumi WATANABE, Naofumi ABIKO
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Publication number: 20190341538Abstract: Some embodiments provide a substrate terminal board in which the number of components is reduced by utilizing a conductor board per se constituting the substrate terminal board while ensuring heat dissipation, and which has a simple structure. Heat-dissipation fins can be cut and raised at a plurality of positions around element mounting portions of an upper-substrate conductor board, thus providing heat-dissipation fins and heat-dissipation openings. The upper-substrate conductor board can be coated with a paint film to form an upper substrate. A lower-substrate conductor board can be coated with the paint film to form a lower substrate. In a pressing/heating process, the lower substrate and the upper substrate can overlap each other and be vertically pressed while the lower substrate and the upper substrate are heated to completely cure the paint film, thereby causing the paint film on the lower substrate and the paint film on the upper substrate to adhere to each other.Type: ApplicationFiled: November 13, 2017Publication date: November 7, 2019Inventors: Masaya NAKAGAWA, Shojiro WAKABAYASHI, Mamoru YUASA, Toshifumi WATANABE
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Patent number: 10444691Abstract: An image forming apparatus includes: an image carrier that carries and transports a latent image; a charging member that is arranged to be in contact with a surface of the image carrier; a developing device that supplies toner to the image carrier and forms a toner image; a density detection unit that detects a density of the toner image; a pattern detection unit that detects a predetermined density variation pattern based on a detection result of the density detection unit according to the toner image; and a determination unit that determines a state of the charging member based on the number of the predetermined density variation patterns detected within a predetermined period of time.Type: GrantFiled: April 28, 2017Date of Patent: October 15, 2019Assignee: KONICA MINOLTA, INC.Inventor: Toshifumi Watanabe
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Publication number: 20190193034Abstract: A gas-dissolved liquid producing apparatus 1 includes a gas supply unit 2, a first liquid supply unit 3, a gas-dissolved liquid generator 4, a second liquid generator 20, a second liquid supply unit 21, a flow rate measuring unit 14, and a controller 23. The controller 23 controls the supply amount of the first liquid to be supplied to the gas-dissolved liquid generator 4 according to the flow rate of circulated gas-dissolved liquid measured by the flow rate measuring unit 14. The gas-dissolved liquid generator 4 dissolves gas supplied from the gas supply unit 2 in first liquid supplied from the first liquid supply unit 3 and second liquid supplied from the second liquid supply unit 21 to generate gas-dissolved liquid.Type: ApplicationFiled: December 19, 2018Publication date: June 27, 2019Inventors: Yoichi NAKAGAWA, Suguru OZAWA, Toshifumi WATANABE, Tao XU
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Publication number: 20180277401Abstract: A substrate processing method which can clean a peripheral portion of a substrate after polishing and can check the cleaning effect of the peripheral portion of the substrate is disclosed. The substrate processing method includes polishing a peripheral portion of the substrate by pressing a polishing tape having abrasive grains against the peripheral portion of the substrate with a first head, cleaning the peripheral portion of the substrate by supplying a cleaning liquid to the peripheral portion of the substrate after polishing, bringing a tape having no abrasive grains into contact with the peripheral portion of the substrate after cleaning by a second head, applying light to the tape and receiving reflected light from the tape by a sensor, and judging that the peripheral portion of the substrate is contaminated when an intensity of the received reflected light is lower than a predetermined value.Type: ApplicationFiled: March 22, 2018Publication date: September 27, 2018Inventors: Toshifumi WATANABE, Satoru YAMAMOTO, Yu MACHIDA
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Publication number: 20180148855Abstract: A method for producing a multi-layer bus bar unit includes preparing a plurality of metal flat plate-shaped bus bars, each with electrode terminal parts at two or more locations, depositing a coating film over an entire surface of each bus bar by electrodeposition coating, subjecting a coating film of a predetermined bus bar to a heating treatment so that the coating film is completely cured, subjecting another bus bar to a heat treatment so that the bus bar is semi-cured, and obtaining a multi-layer structure by alternately overlapping, and then subjecting to a pressure and heating treatment, the bus bar with the completely-cured coating film and the bus bar with the semi-cured coating film, so that the semi-cured coating film is completely cured and the plurality of bus bars adhere to each other by the completely-cured coating film.Type: ApplicationFiled: May 16, 2016Publication date: May 31, 2018Applicants: SUNCALL CORPORATION, STANLEY ELECTRIC CO., LTD.Inventors: Masaya NAKAGAWA, Shojiro WAKABAYASHI, Mamoru YUASA, Toshifumi WATANABE
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Publication number: 20180133861Abstract: To provide a polishing apparatus capable of polishing bevel portions of varying shape by selecting a suitable polishing recipe, based on a state before polishing. The polishing apparatus 100 comprises: a holding/polishing unit 102 for holding and polishing a workpiece W1; and an identifying unit 104 for identifying data 104a associated with a state of the peripheral portion of the substrate W1 before polishing. The holding/polishing unit 102 comprises: a holder 106 for holding and rotating the substrate W1; and a polisher 108 for polishing the peripheral portion of the substrate W1 by pressing a polishing member against the peripheral portion. A polishing-condition determiner 110 determines a polishing condition, based on data 104a indicating to which type, of a plurality of shape-related types, the shape of a given peripheral portion belongs.Type: ApplicationFiled: January 6, 2017Publication date: May 17, 2018Inventors: Masayuki NAKANISHI, Toshifumi WATANABE, Kenji KODERA