Patents by Inventor Toshiharu Tanaka
Toshiharu Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170062713Abstract: According to one embodiment, A memory device includes a pillar, a first wiring, a second wiring, an insulating film provided between the first wiring and the second wiring, a first layer provided between the first wiring and the pillar in the second direction and including a first metal oxide containing a first metal and oxygen, a second layer provided between the second wiring and the pillar in the second direction and including the first metal oxide containing the first metal and oxygen, and an intermediate film provided between the pillar and the first layer and between the pillar and the second layer in the second direction and including a second metal oxide containing the first metal and oxygen. Concentration of oxygen contained in the first metal oxide is lower than concentration of oxygen contained in the second metal oxide.Type: ApplicationFiled: February 2, 2016Publication date: March 2, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Takeshi TAKAGI, Takeshi YAMAGUCHI, Masaki YAMATO, Hiroyuki ODE, Toshiharu TANAKA
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Patent number: 9559300Abstract: In accordance with an embodiment, a resistive random access memory device includes a substrate, first and second wiring lines, and a storage cell. The first and second wiring lines are disposed on the substrate so as to intersect each other. The storage cell is disposed between the first and second wiring lines at the intersection of the first and second wiring lines and includes a first electrode, a resistive switching film on the first electrode, a second electrode on the resistive switching film, and a tantalum oxide (TaOx) layer. The first electrode is electrically connected to the first wiring line. The second electrode is electrically connected to the second wiring line. The tantalum oxide (TaOx) layer is disposed between the first electrode and the resistive switching film and is in contact with the resistive switching film.Type: GrantFiled: August 29, 2014Date of Patent: January 31, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hiroyuki Ode, Takeshi Yamaguchi, Takeshi Takagi, Toshiharu Tanaka, Masaki Yamato
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Publication number: 20170025475Abstract: According to one embodiment, a memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction crossing the first direction and a resistance change film provided between the first wiring and the second wiring. The second wiring includes a first conductive layer and a first intermediate layer including a first region provided between the first conductive layer and the resistance change film. The first intermediate layer includes a material having nonlinear resistance characteristics.Type: ApplicationFiled: February 8, 2016Publication date: January 26, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Takeshi TAKAGI, Takeshi YAMAGUCHI, Masaki YAMATO, Hiroyuki ODE, Toshiharu TANAKA
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Patent number: 9543002Abstract: The transistor layer is disposed above or below the memory layer and includes a transistor. The wiring line layer connects the memory layer and the transistor layer. The memory cell array comprises a plurality of select gate lines connected to gates of a plurality of the select transistors aligned in a third direction. The wiring line layer comprises: a first connecting wiring line connected to a first select gate line of the plurality of select gate lines and extending in the third direction; and a second connecting wiring line connected to a second select gate line adjacent in a second direction to the first select gate line. This second connecting wiring line at least comprises: a first portion extending in the third direction; and a second portion extending from the first portion to a layer below the first connecting wiring line.Type: GrantFiled: August 31, 2015Date of Patent: January 10, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Toshiharu Tanaka
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Publication number: 20160351628Abstract: In this semiconductor memory device, the first conducting layers are arrayed laminated in a first direction, and extend in a second direction intersecting with the first direction. The first conducting layers are arrayed in a third direction via interlayer insulating films. The third direction intersects with the first direction and the second direction. The interlayer insulating film is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer has an approximately circular cross-sectional shape intersecting with the first direction. The variable resistance layer surrounds a peripheral area of the second conducting layer, and is disposed at a position between the second conducting layer and the first conducting layer.Type: ApplicationFiled: December 15, 2015Publication date: December 1, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mutsumi OKAJIMA, Atsushi OGA, Takeshi YAMAGUCHI, Hiroyuki ODE, Toshiharu TANAKA, Natsuki FUKUDA
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Publication number: 20160351624Abstract: According to one embodiment, this semiconductor memory device includes first conducting layers, a memory layer, and second conducting layers. The first conducting layers are laminated at predetermined pitches in a first direction perpendicular to a substrate. The first conducting layers extend in a second direction parallel to the substrate. The second conducting layer extends in the first direction. A memory layer surrounds a circumference of the second conductive layer. The first conductive layers is in contact with a side surface of the second conductive layer via the memory layer. The memory cells are provided at intersections of the first conducting layers and the second conducting layer.Type: ApplicationFiled: September 10, 2015Publication date: December 1, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Atsushi OGA, Mutsumi OKAJIMA, Takeshi YAMAGUCHI, Hiroyuki ODE, Toshiharu TANAKA, Natsuki FUKUDA
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Publication number: 20160267972Abstract: The transistor layer is disposed above or below the memory layer and includes a transistor. The wiring line layer connects the memory layer and the transistor layer. The memory cell array comprises a plurality of select gate lines connected to gates of a plurality of the select transistors aligned in a third direction. The wiring line layer comprises: a first connecting wiring line connected to a first select gate line of the plurality of select gate lines and extending in the third direction; and a second connecting wiring line connected to a second select gate line adjacent in a second direction to the first select gate line. This second connecting wiring line at least comprises: a first portion extending in the third direction; and a second portion extending from the first portion to a layer below the first connecting wiring line.Type: ApplicationFiled: August 31, 2015Publication date: September 15, 2016Applicant: Kabushiki Kaisha ToshibaInventor: Toshiharu TANAKA
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Publication number: 20160260479Abstract: A semiconductor memory device comprises: a memory cell array 11; and a control circuit 16 that controls a voltage applied to the memory cell array 11. The memory cell array 11 includes: a plurality of word lines WL and bit lines BL that intersect each other; and a memory cell MC disposed at each of intersections of these word lines WL and bit lines BL. The memory cell MC includes a variable resistance element VR and a non-ohmic element NO. The variable resistance element VR is formed by a hafnium oxide crystalline film of monoclinic crystal in which a proportion of a component oriented in a (?1, 1, 1) plane and a (1, 1, 1) plane is 90% or more. This hafnium oxide crystalline film can be manufactured by a film-forming process by atomic layer deposition, employing an inorganic type hafnium precursor.Type: ApplicationFiled: September 3, 2015Publication date: September 8, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroyuiki ODE, Takeshi YAMAGUCHI, Takeshi TAKAGI, Toshiharu TANAKA, Masaki YAMATO
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Patent number: 9418737Abstract: A nonvolatile semiconductor memory device includes: a memory cell array; and a control circuit that controls a voltage applied to this memory cell array. The memory cell array includes: a first wiring line; a second wiring line intersecting the first wiring line; and a memory cell disposed at an intersection of these lines and including a variable resistance element. In a rewrite operation of the memory cell, the control circuit repeatedly perform a pulse application operation and a verify operation, the pulse application operation applying a pulse voltage to the memory cell, and the verify operation applying a first voltage to the memory cell to determine whether the rewrite operation has been completed or not. The control circuit is configured to, in a read operation from the memory cell, apply a second voltage to the memory cell. The second voltage has a voltage value larger than the first voltage.Type: GrantFiled: July 30, 2015Date of Patent: August 16, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Takeshi Takagi, Masaki Yamato, Hiroyuki Ode, Takeshi Yamaguchi, Toshiharu Tanaka
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Publication number: 20160189776Abstract: A nonvolatile semiconductor memory device includes: a memory cell array; and a control circuit that controls a voltage applied to this memory cell array. The memory cell array includes: a first wiring line; a second wiring line intersecting the first wiring line; and a memory cell disposed at an intersection of these lines and including a variable resistance element. In a rewrite operation of the memory cell, the control circuit repeatedly perform a pulse application operation and a verify operation, the pulse application operation applying a pulse voltage to the memory cell, and the verify operation applying a first voltage to the memory cell to determine whether the rewrite operation has been completed or not. The control circuit is configured to, in a read operation from the memory cell, apply a second voltage to the memory cell. The second voltage has a voltage value larger than the first voltage.Type: ApplicationFiled: July 30, 2015Publication date: June 30, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takeshi TAKAGI, Masaki YAMATO, Hiroyuki ODE, Takeshi YAMAGUCHI, Toshiharu TANAKA
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Patent number: 9362168Abstract: According to an embodiment, a non-volatile memory device includes a first wiring provided on an underlayer, a first memory cell array provided on the first wiring and including a plurality of memory cells, a first select element including a first control electrode provided between the first wiring and the first memory cell array. The device also includes a second wiring provided at the same level as the first wiring and electrically connected to the first control electrode, and a first plug electrically connecting the first control electrode and the second wiring, one end of the first plug being in contact with the second wiring, and a side surface of the first plug being in contact with the first control electrode.Type: GrantFiled: January 8, 2014Date of Patent: June 7, 2016Assignee: Kabushiki Kaisha ToshibaInventor: Toshiharu Tanaka
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Patent number: 9336880Abstract: A nonvolatile memory device comprises a memory cell comprising a variable resistance element connected between a couple of wirings and a control circuit applying a voltage between the couple of wirings connected to the memory cell. In data rewriting, the control circuit repeats a first voltage application step of applying a first write voltage between the couple of wirings and a first verify step of applying a first voltage lower than the first write voltage between the couple of wirings and comparing a cell current through the cell with a first threshold current, the steps repeated until a magnitude relation of the cell current and the first threshold current satisfies a first condition. If the first condition is satisfied, the circuit performs a second voltage application step of applying a second write voltage between the couple of wirings.Type: GrantFiled: March 2, 2015Date of Patent: May 10, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Takeshi Takagi, Masaki Yamato, Hiroyuki Ode, Takeshi Yamaguchi, Toshiharu Tanaka
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Publication number: 20160019959Abstract: A nonvolatile memory device comprises a memory cell comprising a variable resistance element connected between a couple of wirings and a control circuit applying a voltage between the couple of wirings connected to the memory cell. In data rewriting, the control circuit repeats a first voltage application step of applying a first write voltage between the couple of wirings and a first verify step of applying a first voltage lower than the first write voltage between the couple of wirings and comparing a cell current through the cell with a first threshold current, the steps repeated until a magnitude relation of the cell current and the first threshold current satisfies a first condition. If the first condition is satisfied, the circuit performs a second voltage application step of applying a second write voltage between the couple of wirings.Type: ApplicationFiled: March 2, 2015Publication date: January 21, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Takeshi TAKAGI, Masaki Yamato, Hiroyuki Ode, Takeshi Yamaguchi, Toshiharu Tanaka
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Publication number: 20150369779Abstract: A welding state inspection method for ultrasonic-welded plate-like members includes the steps of measuring energy that has been transmitted to an anvil when ultrasonic-welding a plurality of plate-like members stacked on the anvil while pressing a horn that vibrates against the plate-like members; and determining a quality of a welding state of the plate-like members on the basis of the energy measured in the measuring step.Type: ApplicationFiled: December 25, 2013Publication date: December 24, 2015Applicants: NISSAN MOTOR CO., LTD., AUTOMOTIVE ENERGY SUPPLY CORPORATIONInventors: Koichi KAWAMOTO, Shuji YOSHIDA, Yutaka SUZUKI, Takashi MATSUOKA, Toshiharu TANAKA
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Patent number: 9166164Abstract: A method for manufacturing a nonvolatile semiconductor storage device according to an embodiment includes laminating a first wire extending in a first direction, and a film made into a variable resistance element made of a metallic material, which are laminated in order on a semiconductor substrate, dividing, into a plurality of pieces, the film made into the variable resistance element, in the first direction and a second direction, forming an interlayer insulating film between the plurality of pieces formed by dividing the film made into the variable resistance element in the second direction, and oxidizing the metallic material of the film made into the variable resistance element, and laminating an upper electrode and a second wire extending in the second direction, which are laminated in order on the film made into the variable resistance element and the interlayer insulating film.Type: GrantFiled: September 10, 2014Date of Patent: October 20, 2015Assignee: KABUSHIKI KAISHAInventor: Toshiharu Tanaka
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Publication number: 20150189476Abstract: There is provided an information processing system including an acquisition section configured to acquire a movement direction and a movement purpose from each one of a plurality of terminal devices; and a guide information issuing section configured to issue a guide information which is generate based on the movement direction and the movement purpose of the a plurality of terminal devices.Type: ApplicationFiled: September 11, 2013Publication date: July 2, 2015Applicant: Sony CorporationInventor: Toshiharu Tanaka
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Publication number: 20150083989Abstract: In accordance with an embodiment, a resistive random access memory device includes a substrate, first and second wiring lines, and a storage cell. The first and second wiring lines are disposed on the substrate so as to intersect each other. The storage cell is disposed between the first and second wiring lines at the intersection of the first and second wiring lines and includes a first electrode, a resistive switching film on the first electrode, a second electrode on the resistive switching film, and a tantalum oxide (TaOx) layer. The first electrode is electrically connected to the first wiring line. The second electrode is electrically connected to the second wiring line. The tantalum oxide (TaOx) layer is disposed between the first electrode and the resistive switching film and is in contact with the resistive switching film.Type: ApplicationFiled: August 29, 2014Publication date: March 26, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroyuki ODE, Takeshi Yamaguchi, Takeshi Takagi, Toshiharu Tanaka, Masaki Yamato
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Publication number: 20150062993Abstract: According to an embodiment, a non-volatile memory device includes a first wiring provided on an underlayer, a first memory cell array provided on the first wiring and including a plurality of memory cells, a first select element including a first control electrode provided between the first wiring and the first memory cell array. The device also includes a second wiring provided at the same level as the first wiring and electrically connected to the first control electrode, and a first plug electrically connecting the first control electrode and the second wiring, one end of the first plug being in contact with the second wiring, and a side surface of the first plug being in contact with the first control electrode.Type: ApplicationFiled: January 8, 2014Publication date: March 5, 2015Applicant: Kabushiki Kaisha ToshibaInventor: Toshiharu TANAKA
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Patent number: 8920150Abstract: A pin having a light guide for an injection mold includes an outer sleeve having a hollow portion, an inner sleeve fixed to the hollow portion of the outer sleeve, a bundle sleeve fixed to a hollow portion of the inner sleeve, a bundle fiber fixed to a hollow portion of the bundle sleeve. A leading end portion of the bundle sleeve has a substantially cone-shaped caulked portion. A portion of the hollow portion of the inner sleeve which is brought into contact with the cone-shaped caulked portion of the bundle sleeve has a tapered shape that coincides with the shape of the portion of the bundle sleeve. A shoulder portion is formed at a rear end portion of the hollow portion of the outer sleeve and a rear end of the inner sleeve is engage with the shoulder portion.Type: GrantFiled: December 17, 2013Date of Patent: December 30, 2014Assignee: Futaba CorporationInventors: Toshiharu Tanaka, Yasuhiro Nohara
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Publication number: 20140377932Abstract: A method for manufacturing a nonvolatile semiconductor storage device according to an embodiment includes laminating a first wire extending in a first direction, and a film made into a variable resistance element made of a metallic material, which are laminated in order on a semiconductor substrate, dividing, into a plurality of pieces, the film made into the variable resistance element, in the first direction and a second direction, forming an interlayer insulating film between the plurality of pieces formed by dividing the film made into the variable resistance element in the second direction, and oxidizing the metallic material of the film made into the variable resistance element, and laminating an upper electrode and a second wire extending in the second direction, which are laminated in order on the film made into the variable resistance element and the interlayer insulating film.Type: ApplicationFiled: September 10, 2014Publication date: December 25, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Toshiharu TANAKA