Abstract: A nonvolatile semiconductor memory includes rewritable nonvolatile memory cell transistors connected in series. The nonvolatile memory cell transistors includes at least two charge storage layers formed on a first insulating film, a control gate shared by two adjacent transistors which are two of the nonvolatile memory cell transistors and which are adjacent to each other, and a second insulating film formed between the at least two charge storage layers and the control gate. A top of the control gate has a flat surface that covers the at least two charge storage layers that correspond to the two adjacent transistors, and the flat surface extends from one of the at least two charge storage layers to the other of the at least two charge storage layers.

Abstract: A non-volatile semiconductor memory device comprising a device isolation insulation layer, formed on a semiconductor substrate, for defining a device region, a floating gate formed on the device region and having a pair of first side faces opposed to a side face of the device isolation insulation layer, which the side face is located on the device region side, a control gate formed above the floating gate, and a booster electrode having faces opposed to a pair of second surfaces which are substantially perpendicular to the pair of first side faces. A distance between the pair of first side faces of the floating gate is less than a width of the device region defined by the device isolation insulation layer.

Abstract: A trench region 14 is formed in a memory cell P-type well 13. Two NAND-type memory cell units ND1 and ND2 are respectively formed along both side wall portions of this trench region 14. A floating gate FG and a control gate CG in these NAND-type memory cell units ND1 and ND2 are formed self-aligningly without using a photoresist. One bit line BL connected to the two NAND-type memory cell units ND1 and ND2 is formed via an interlayer dielectric 30. The bit line pitch of this bit line BL is set at 2 F. Hence, the size of a nonvolatile semiconductor memory can be reduced.

Abstract: A first side-wall film is formed on the sides of a gate electrode of a high-voltage transistor, and a second side-wall film is provided on the first side-wall film. The first side-wall film has an etching rate lower that of a pre-metal dielectric, and the second side-wall film has an etching rate substantially equal to that of the of the pre-metal dielectric. The LDD of the high-voltage transistor is provided in that part of the semiconductor substrate which lies right below the first and second side-wall films. The source/drain diffusion layer of the high-voltage transistor is formed in that part of the substrate which is outside the second side-wall film. A first side-wall film having an etching rate lower than that of the pre-metal dielectric and/or a second side-wall film having an etching rate substantially equal to that of the pre-metal dielectric are provided on the sides of the gate electrode of the low voltage transistor.

Abstract: A trench region is formed in a memory cell P-type well. Two NAND-type memory cell units are respectively formed along both side wall portions of this trench region. A floating gate and a control gate in these NAND-type memory cell units are formed self-aligningly without using a photoresist. One bit line connected to the two NAND-type memory cell units is formed via an interlayer dielectric. The bit line pitch of this bit line is set at 2 F. Hence, the size of a nonvolatile semiconductor memory can be reduced.

Abstract: A non-volatile semiconductor memory device comprising a device isolation insulation layer, formed on a semiconductor substrate, for defining a device region, a floating gate formed on the device region and having a pair of first side faces opposed to a side face of the device isolation insulation layer, which the side face is located on the device region side, a control gate formed above the floating gate, and a booster electrode having faces opposed to a pair of second surfaces which are substantially perpendicular to the pair of first side faces. A distance between the pair of first side faces of the floating gate is less than a width of the device region defined by the device isolation insulation layer.

Abstract: A structure of at least a stationary-side race of a bearing is transformed into a lower bainite structure through an isothermal transformation treatment. Furthermore, the adjustment is made for hardness to HRC=54 to 64, an amount of residual austenite to not more than 5% and an area percentage of 0.8 &mgr;m or longer carbide to not more than 20% based on the total area of secondary carbide. Thus is prevented the occurrence of a white layer in the rolling bearing.

Abstract: A cooling cycle with a high-pressure side operating in a supercritical area of refrigerant includes a temperature sensor for sensing a temperature of cooled refrigerant between a gas cooler and an internal heat exchanger, a pressure sensor for sensing a pressure of cooled refrigerant between the two, and a controller for controlling at least one of a compressor and a throttling device in accordance with the sensed temperature and the sensed pressure.

Abstract: A non-volatile semiconductor memory device comprising a device isolation insulation layer, a floating gate, and control gate, and a booster electrode. The device isolation insulation layer is formed on a semiconductor substrate, and is for defining a device region. The floating gate is formed above the device region and has a pair of first side faces opposed to a side face of the device isolation insulation layer which is located on the device region side. The control gate is formed above the floating gate. The booster electrode has faces opposed to a pair of second surfaces of the floating gate which are substantially perpendicular to the pair of first side faces. A distance between the pair of first side faces of the floating gate is equal or not more than a width of the device region defined by the device isolation insulation layer. Dimensions of the floating gate are determined based on a coupling ratio between the floating gate and the booster electrode.

Abstract: In a cooling cycle including a compressor, a gas cooler, a throttling device, and an evaporator, a heat exchanger is arranged between the compressor and the throttling device for carrying out heat exchange through a refrigerant compressed by the compressor.

Abstract: A steering apparatus for a vehicle has: a steering shaft rotatable with a steering force applied from a steering wheel; a cable unit for transmitting a rotational force with an output member and a pair of cable wires; and a speed reducing gear disposed between the steering shaft and the cable unit. The output member makes a rotation in such a manner that the pair of the cable wires are pulled relative to each other. The rotational force is transmitted from the steering shaft to a side having a tire-and-wheel.

Abstract: A first side-wall film is formed on the sides of a gate electrode of a high-voltage transistor, and a second side-wall film is provided on the first side-wall film. The first side-wall film has an etching rate lower that of a pre-metal dielectric, and the second side-wall film has an etching rate substantially equal to that of the of the pre-metal dielectric. The LDD of the high-voltage transistor is provided in that part of the semiconductor substrate which lies right below the first and second side-wall films. The source/drain diffusion layer of the high-voltage transistor is formed in that part of the substrate which is outside the second side-wall film. A first side-wall film having an etching rate lower than that of the pre-metal dielectric and/or a second side-wall film having an etching rate substantially equal to that of the pre-metal dielectric are provided on the sides of the gate electrode of the low voltage transistor.

Abstract: To provide a cockpit module structure for a vehicle where large foot space and a secure and stable supported state can be secured, the body of an air conditioning unit inside which heat exchangers and opening and closing doors are installed is penetrated by a steering member.

Abstract: A cooling cycle with a high-pressure side operating in a supercritical area of refrigerant includes a temperature sensor for sensing a temperature of cooled refrigerant between a gas cooler and an internal heat exchanger, a pressure sensor for sensing a pressure of cooled refrigerant between the two, and a controller for controlling at least one of a compressor and a throttling device in accordance with the sensed temperature and the sensed pressure.

Abstract: A first side-wall film is formed on the sides of a gate electrode of a high-voltage transistor, and a second side-wall film is provided on the first side-wall film. The first side-wall film has an etching rate lower that of a pre-metal dielectric, and the second side-wall film has an etching rate substantially equal to that of the of the pre-metal dielectric. The LDD of the high-voltage transistor is provided in that part of the semiconductor substrate which lies right below the first and second side-wall films. The source/drain diffusion layer of the high-voltage transistor is formed in that part of the substrate which is outside the second side-wall film. A first side-wall film having an etching rate lower than that of the pre-metal dielectric and/or a second side-wall film having an etching rate substantially equal to that of the pre-metal dielectric are provided on the sides of the gate electrode of the low voltage transistor.

Abstract: A nonvolatile semiconductor memory device comprises a semiconductor substrate, element isolating regions provided in the semiconductor substrate, first element regions, each of which is defined by two adjacent ones of the element isolating regions, and memory cell transistors formed in the element regions, wherein each of the memory cell transistors comprises a first gate insulating film formed on a corresponding one of the element isolating regions, a floating gate electrode formed on the gate insulating film, a second gate insulating film formed on the floating gate electrode, and a control electrode formed on the second gate insulating film and connected in common to a specific number of ones of the memory cell transistors to serve as a word line, and the floating gate includes a first conductive member with side faces in contact with side ends of the two adjacent ones of the element isolating regions and a second conductive member electrically connected to the first conductive member and formed so as to b

Abstract: A nonvolatile semiconductor memory device comprises a semiconductor substrate, element isolating regions provided in the semiconductor substrate, first element regions, each of which is defined by two adjacent ones of the element isolating regions, and memory cell transistors formed in the element regions, wherein each of the memory cell transistors comprises a first gate insulating film formed on a corresponding one of the element isolating regions, a floating gate electrode formed on the gate insulating film, a second gate insulating film formed on the floating gate electrode, and a control electrode formed on the second gate insulating film and connected in common to a specific number of ones of the memory cell transistors to serve as a word line, and the floating gate includes a first conductive member with side faces in contact with side ends of the two adjacent ones of the element isolating regions and a second conductive member electrically connected to the first conductive member and formed so as to b

Abstract: A first side-wall film is formed on the sides of a gate electrode of a high-voltage transistor, and a second side-wall film is provided on the first sidewall film. The first side-wall film has an etching rate lower that of a pre-metal dielectric, and the second side-wall film has an etching rate substantially equal to that of the of the pre-metal dielectric. The LDD of the high-voltage transistor is provided in that part of the semiconductor substrate which lies right below the first and second side-wall films. The source/drain diffusion layer of the high-voltage transistor is formed in that part of the substrate which is outside the second side-wall film. A first side-wall film having an etching rate lower than that of the pre-metal dielectric and/or a second side-wall film having an etching rate substantially equal to that of the pre-metal dielectric are provided on the sides of the gate electrode of the low voltage transistor.

Abstract: A non-volatile semiconductor memory device comprising a device isolation insulation layer, formed on a semiconductor substrate, for defining a device region, a floating gate formed on the device region and having a pair of first side faces opposed to a side face of the device isolation insulation layer, which the side face is located on the device region side, a control gate formed above the floating gate, and a booster electrode having faces opposed to a pair of second surfaces which are substantially perpendicular to the pair of first side faces. A distance between the pair of first side faces of the floating gate is less than a width of the device region defined by the device isolation insulation layer.

Abstract: A trench region 14 is formed in a memory cell P-type well 13. Two NAND-type memory cell units ND1 and ND2 are respectively formed along both side wall portions of this trench region 14. A floating gate FG and a control gate CG in these NAND-type memory cell units ND1 and ND2 are formed self-aligningly without using a photoresist. One bit line BL connected to the two NAND-type memory cell units ND1 and ND2 is formed via an interlayer dielectric 30. The bit line pitch of this bit line BL is set at 2 F. Hence, the size of a nonvolatile semiconductor memory can be reduced.