Patents by Inventor Toshihide Kikkawa

Toshihide Kikkawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9224848
    Abstract: An AlGaN/GaN.HEMT includes, a compound semiconductor lamination structure; a p-type semiconductor layer formed on the compound semiconductor lamination structure; and a gate electrode formed on the p-type semiconductor layer, in which Mg being an inert element of p-GaN is introduced into both sides of the gate electrode at the p-type semiconductor layer, and introduced portions of Mg are inactivated.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: December 29, 2015
    Assignee: Transphorm Japan, Inc.
    Inventor: Toshihide Kikkawa
  • Publication number: 20150333135
    Abstract: A compound semiconductor device includes: a compound semiconductor layer; a protective insulating film that covers a top of the compound semiconductor layer; and a gate electrode formed on the protective insulating film, wherein the protective insulating film has a first trench and a second trench which is formed side by side with the first trench and in which the protective insulating film remains with only a predetermined thickness on the compound semiconductor layer, and wherein the gate electrode fills the first trench, and one end of the gate electrode is away from the first trench and located at least in the second trench.
    Type: Application
    Filed: July 29, 2015
    Publication date: November 19, 2015
    Inventors: Kozo MAKIYAMA, Naoya Okamoto, Toshihide Kikkawa
  • Patent number: 9184272
    Abstract: A compound semiconductor device includes: a compound semiconductor layer; a protective insulating film that covers a top of the compound semiconductor layer; and a gate electrode formed on the protective insulating film, wherein the protective insulating film has a first trench and a second trench which is formed side by side with the first trench and in which the protective insulating film remains with only a predetermined thickness on the compound semiconductor layer, and wherein the gate electrode fills the first trench, and one end of the gate electrode is away from the first trench and located at least in the second trench.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: November 10, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Kozo Makiyama, Naoya Okamoto, Toshihide Kikkawa
  • Publication number: 20150279956
    Abstract: A semiconductor device includes a first semiconductor layer formed over a substrate, a second semiconductor layer formed over the first semiconductor layer, a source electrode and a drain electrode formed over the second semiconductor layer, an insulating film formed over the second semiconductor layer, a gate electrode formed over the insulating film, and a protection film covering the insulating film, the protection film being formed by thermal CVD, thermal ALD, or vacuum vapor deposition.
    Type: Application
    Filed: June 9, 2015
    Publication date: October 1, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Masahito Kanamura, Norikazu Nakamura, Toyoo Miyajima, Masayuki Takeda, Keiji Watanabe, Toshihide Kikkawa, Kenji Imanishi, Toshihiro Ohki, Tadahiro Imada
  • Patent number: 9147761
    Abstract: The compound semiconductor device comprises an i-GaN buffer layer 12 formed on an SiC substrate 10; an n-AlGaN electron supplying layer 16 formed on the i-GaN buffer layer 12; an n-GaN cap layer 18 formed on the n-AlGaN electron supplying layer 16; a source electrode 20 and a drain electrode 22 formed on the n-GaN cap layer 18; a gate electrode 26 formed on the n-GaN cap layer 18 between the source electrode 20 and the drain electrode 22; a first protection layer formed on the n-GaN cap layer 18 between the source electrode 20 and the drain electrode 22; and a second protection layer 30 buried in an opening 28 formed in the first protection layer 24 between the gate electrode 26 and the drain electrode 22 down to the n-GaN cap layer 18 and formed of an insulation film different from the first protection layer.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: September 29, 2015
    Assignee: FUJITSU LIMITED
    Inventor: Toshihide Kikkawa
  • Patent number: 9142658
    Abstract: A compound semiconductor device includes: a compound semiconductor layer; and a gate electrode formed above the compound semiconductor layer; and a source electrode and a drain electrode formed on both sides of the gate electrode, on the compound semiconductor layer, wherein the source electrode has a plurality of bottom surfaces along transit electrons out of contact surfaces with the compound semiconductor layer, and the plural bottom surfaces are located at different distances from the transit electrons, with the bottom surface closer to the gate electrode being more apart from the transit electrons.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: September 22, 2015
    Assignee: Transphorm Japan, Inc.
    Inventors: Toshihide Kikkawa, Kenji Nukui
  • Patent number: 9034722
    Abstract: A method for manufacturing a compound semiconductor device so as to separate a first substrate from a compound semiconductor laminated structure which includes forming a first compound semiconductor layer over a first substrate containing AlxGa1-xN (0?x<1) and having a first band gap; forming a second compound semiconductor layer over the first compound semiconductor layer containing AlyInzGa1-y-zN (0<y<1, 0<y+z?1) and having a second band gap larger than the first band gap; forming a compound semiconductor laminated structure over the second compound semiconductor layer; and removing the first compound semiconductor layer while irradiating the first compound semiconductor layer with light having an energy between the first band gap and the second band gap, and thereby separating the first substrate from the compound semiconductor laminated structure.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: May 19, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Yuichi Minoura, Toshihide Kikkawa
  • Publication number: 20150129888
    Abstract: A semiconductor device includes: a first nitride semiconductor layer formed over a substrate; a second nitride semiconductor layer formed over the first nitride semiconductor layer; element isolation regions formed in a part of the second nitride semiconductor layer and the first nitride semiconductor layer; a gate electrode, source electrodes, and a drain electrode formed over the second semiconductor layer and the element isolation regions; and a drain field plate formed in such a manner as to project from upper portions of side surfaces of the drain electrode.
    Type: Application
    Filed: October 20, 2014
    Publication date: May 14, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Masato Nishimori, Toshihide Kikkawa
  • Publication number: 20150078038
    Abstract: An AlGaN/GaN.HEMT includes, a compound semiconductor lamination structure; a p-type semiconductor layer formed on the compound semiconductor lamination structure; and a gate electrode formed on the p-type semiconductor layer, in which Mg being an inert element of p-GaN is introduced into both sides of the gate electrode at the p-type semiconductor layer, and introduced portions of Mg are inactivated.
    Type: Application
    Filed: December 5, 2014
    Publication date: March 19, 2015
    Inventor: Toshihide Kikkawa
  • Patent number: 8969159
    Abstract: A first AlGaN layer formed over a substrate, a second AlGaN layer formed over the first AlGaN layer, an electron transit layer formed over the second AlGaN layer, and an electron supply layer formed over the electron transit layer are provided. A relationship of “0?x1<x2?1” is found when a composition of the first AlGaN layer is represented by Alx1Ga1-x1N, and a composition of the second AlGaN layer is represented by Alx2Ga1-x2N. Negative charges exist at an upper surface of the AlGaN layer more than positive charges existing at a lower surface of the AlGaN layer.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: March 3, 2015
    Assignee: Fujitsu Limited
    Inventors: Kenji Imanishi, Toshihide Kikkawa
  • Publication number: 20150041860
    Abstract: A semiconductor device includes an electron transit layer configured to be formed on a substrate; an electron supply layer configured to be formed on the electron transit layer; an upper surface layer configured to be formed on the electron supply layer; a gate electrode configured to be formed on the electron supply layer or the upper surface layer; a source electrode and a drain electrode configured to be formed on the upper surface layer; and first conductivity-type regions configured to be formed in the upper surface layer and the electron supply layer immediately below regions where the source electrode and the drain electrode are formed. The electron supply layer is formed of a nitride semiconductor including In. The upper surface layer is formed of a material including a nitride of one or more elements selected among B, Al, and Ga.
    Type: Application
    Filed: July 29, 2014
    Publication date: February 12, 2015
    Inventors: Masato Nishimori, Toshihide Kikkawa
  • Patent number: 8933489
    Abstract: An AlGaN/GaN.HEMT includes, a compound semiconductor lamination structure; a p-type semiconductor layer formed on the compound semiconductor lamination structure; and a gate electrode formed on the p-type semiconductor layer, in which Mg being an inert element of p-GaN is introduced into both sides of the gate electrode at the p-type semiconductor layer, and introduced portions of Mg are inactivated.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: January 13, 2015
    Assignee: Transphorm Japan, Inc.
    Inventor: Toshihide Kikkawa
  • Patent number: 8912571
    Abstract: A compound semiconductor device includes: a compound semiconductor layer; a first film formed over the compound semiconductor layer, the first film being in a negatively charged state or a non-charged state at an interface with the compound semiconductor layer; a second film formed over the first film, the second film being in a positively charged state at an interface with the first film; and a gate electrode to be embedded in an opening formed in the second film.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: December 16, 2014
    Assignee: Fujitsu Limited
    Inventors: Masahito Kanamura, Toshihide Kikkawa, Kenji Imanishi
  • Publication number: 20140353681
    Abstract: The compound semiconductor device comprises an i-GaN buffer layer 12 formed on an SiC substrate 10; an n-AlGaN electron supplying layer 16 formed on the i-GaN buffer layer 12; an n-GaN cap layer 18 formed on the n-AlGaN electron supplying layer 16; a source electrode 20 and a drain electrode 22 formed on the n-GaN cap layer 18; a gate electrode 26 formed on the n-GaN cap layer 18 between the source electrode 20 and the drain electrode 22; a first protection layer formed on the n-GaN cap layer 18 between the source electrode 20 and the drain electrode 22; and a second protection layer 30 buried in an opening 28 formed in the first protection layer 24 between the gate electrode 26 and the drain electrode 22 down to the n-GaN cap layer 18 and formed of an insulation film different from the first protection layer.
    Type: Application
    Filed: August 15, 2014
    Publication date: December 4, 2014
    Inventor: Toshihide Kikkawa
  • Patent number: 8901610
    Abstract: The compound semiconductor device comprises an i-GaN buffer layer 12 formed on an SiC substrate 10; an n-AlGaN electron supplying layer 16 formed on the i-GaN buffer layer 12; an n-GaN cap layer 18 formed on the n-AlGaN electron supplying layer 16; a source electrode 20 and a drain electrode 22 formed on the n-GaN cap layer 18; a gate electrode 26 formed on the n-GaN cap layer 18 between the source electrode 20 and the drain electrode 22; a first protection layer 24 formed on the n-GaN cap layer 18 between the source electrode 20 and the drain electrode 22; and a second protection layer 30 buried in an opening 28 formed in the first protection layer 24 between the gate electrode 26 and the drain electrode 22 down to the n-GaN cap layer 18 and formed of an insulation film different from the first protection layer.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: December 2, 2014
    Assignee: Fujitsu Limited
    Inventor: Toshihide Kikkawa
  • Patent number: 8896022
    Abstract: A compound semiconductor device has a buffer layer formed on a conductive SiC substrate, an AlxGa1-xN layer formed on the buffer layer in which an impurity for reducing carrier concentration from an unintentionally doped donor impurity is added and in which the Al composition x is 0<x<1, a GaN-based carrier transit layer formed on the AlxGa1-xN layer, a carrier supply layer formed on the carrier transit layer, a source electrode and a drain electrode formed on the carrier supply layer, and a gate electrode formed on the carrier supply layer between the source electrode and the drain electrode. Therefore, a GaN-HEMT that is superior in device characteristics can be realized in the case of using a relatively less expensive conductive SiC substrate compared with a semi-insulating SiC substrate.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: November 25, 2014
    Assignee: Fujitsu Limited
    Inventors: Kenji Imanishi, Toshihide Kikkawa
  • Patent number: 8866157
    Abstract: A semiconductor device may include a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, a source electrode and a drain electrode in contact with the first semiconductor layer or the second semiconductor layer, an opening formed in the second semiconductor layer, an insulating film formed on an inner surface of the opening formed in the second semiconductor layer and above the second semiconductor layer, a gate electrode formed in the opening via the insulating film, and a protective film formed on the insulating film and including an amorphous film containing carbon as a major component.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: October 21, 2014
    Assignee: Fujitsu Limited
    Inventors: Norikazu Nakamura, Shirou Ozaki, Masayuki Takeda, Toyoo Miyajima, Toshihiro Ohki, Masahito Kanamura, Kenji Imanishi, Toshihide Kikkawa, Keiji Watanabe
  • Patent number: 8841706
    Abstract: An AlN layer (2), a GaN buffer layer (3), a non-doped AlGaN layer (4a), an n-type AlGaN layer (4b), an n-type GaN layer (5), a non-doped AlN layer (6) and an SiN layer (7) are sequentially formed on an SiC substrate (1). At least three openings are formed in the non-doped AlN layer (6) and the SiN layer (7), and a source electrode (8a), a drain electrode (8b) and a gate electrode (19) are evaporated in these openings.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: September 23, 2014
    Assignee: Fujitsu Limited
    Inventor: Toshihide Kikkawa
  • Patent number: 8816408
    Abstract: A compound semiconductor device includes a compound semiconductor laminated structure; a source electrode, a drain electrode, and a gate electrode formed over the compound semiconductor laminated structure; a first protective film formed over the compound semiconductor laminated structure between the source electrode and the gate electrode and including silicon; and a second protective film formed over the compound semiconductor laminated structure between the drain electrode and the gate electrode and including more silicon than the first protective film.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: August 26, 2014
    Assignee: Fujitsu Limited
    Inventors: Kozo Makiyama, Toshihide Kikkawa
  • Patent number: 8765554
    Abstract: A gate electrode is formed so as to embed an electrode material in a recess for an electrode, which has been formed in a structure of stacked compound semiconductors, through a gate insulation film, and also a field plate electrode that comes in Schottky contact with the structure of the stacked compound semiconductors is formed by embedding an electrode material in a recess for an electrode, which has been formed in the structure of the stacked compound semiconductors so that the field plate electrode directly comes in contact with the structure of the stacked compound semiconductors at least on the bottom face of the recess for the electrode.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: July 1, 2014
    Assignee: Fujitsu Limited
    Inventors: Tadahiro Imada, Toshihide Kikkawa