Patents by Inventor Toshihide Nabatame

Toshihide Nabatame has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11486843
    Abstract: The present invention is to provide a small-sized dryness/wetness responsive sensor that detects a galvanic current with a high sensitivity as a principle of operation. According to one embodiment of the present invention, a dryness/wetness responsive sensor comprises a thin wire made of a first metal and a thin wire made of a second metal, the second metal is different from the first metal, the thin wire of the first metal and the thin wire of the second metal are disposed in juxtaposition with each other on an insulating substrate, and a surface state of a part between the thin wire of the first metal and the thin wire of the second metal is hydrophilic or hydrophobic.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: November 1, 2022
    Assignee: NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Jin Kawakita, Akihiko Ohi, Tomoko Ohki, Naoki Ikeda, Toshihide Nabatame, Toyohiro Chikyo
  • Patent number: 10290802
    Abstract: The forming voltage of a variable resistance device used in a non-volatile memory and the like is decreased, and repetition characteristics are improved. In an element structure in which a metal oxide film is sandwiched between a lower electrode and an upper electrode, an island-shaped/particulate region of amorphous aluminum oxide or aluminum oxycarbide is formed on the metal oxide film. Because an oxide deficiency, serving as the nucleus of a filament for implementing an on/off operation of the variable resistance device, is formed from the beginning under the island-shaped or particulate aluminum oxide or the like, the conventional creation of an oxide deficiency by high-voltage application in the initial period of forming can be eliminated. Such a region can be fabricated using a small number of cycles of an ALD process.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: May 14, 2019
    Assignee: National Insitute for Materials Science
    Inventors: Toshihide Nabatame, Tadaaki Nagao
  • Patent number: 10267756
    Abstract: A dryness/wetness responsive sensor having decreased size, and improved sensitivity and responsiveness. The present invention comprises a thin wire of a first metal and a thin wire of a second metal, which is different from the first metal, wherein the thin wires run in juxtaposition with each other on an insulating substrate, and wherein the spacing between the first thin wire and the second thin wire is in the range of 5 nm or more and less than 20 ?m.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: April 23, 2019
    Assignee: NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Jin Kawakita, Tadashi Shinohara, Toyohiro Chikyo, Toshihide Nabatame, Akihiko Ohi, Tomoko Ohki
  • Patent number: 9825180
    Abstract: The present invention provides a thin-film transistor in which transistor characteristics such as drain current and threshold voltage are improved, and a method of manufacturing the same. The present invention provides a thin-film transistor provided with a source electrode (108), a drain electrode (109), a semiconductor layer (105), a gate electrode (103), and an insulating layer (104); wherein the semiconductor layer (105) contains a composite metal oxide obtained by adding to a first metal oxide an oxide having an oxygen dissociation energy that is at least 200 kJ/mol greater than the oxygen dissociation energy of the first metal oxide, whereby the amount of oxygen vacancy is controlled; and the insulating layer (104) is provided with an SiO2 layer, a high-permittivity first layer, and a high-permittivity second layer, whereby the dipoles generated at the boundary between the SiO2 layer and the high-permittivity layers are used to control the threshold voltage.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: November 21, 2017
    Assignee: National Institute for Materials Science
    Inventors: Toshihide Nabatame, Kazuhito Tsukagoshi, Shinya Aikawa, Toyohiro Chikyo
  • Patent number: 9741864
    Abstract: The present invention provides a thin-film transistor in which transistor characteristics such as drain current and threshold voltage are improved, and a method of manufacturing the same. The present invention provides a thin-film transistor provided with a source electrode (108), a drain electrode (109), a semiconductor layer (105), a gate electrode (103), and an insulating layer (104); wherein the semiconductor layer (105) contains a composite metal oxide obtained by adding to a first metal oxide an oxide having an oxygen dissociation energy that is at least 200 kJ/mol greater than the oxygen dissociation energy of the first metal oxide, whereby the amount of oxygen vacancy is controlled; and the insulating layer (104) is provided with an SiO2 layer, a high-permittivity first layer, and a high-permittivity second layer, whereby the dipoles generated at the boundary between the SiO2 layer and the high-permittivity layers are used to control the threshold voltage.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: August 22, 2017
    Assignee: National Institute for Materials Science
    Inventors: Toshihide Nabatame, Kazuhito Tsukagoshi, Shinya Aikawa
  • Publication number: 20160365455
    Abstract: The present invention provides a thin-film transistor in which transistor characteristics such as drain current and threshold voltage are improved, and a method of manufacturing the same. The present invention provides a thin-film transistor provided with a source electrode (108), a drain electrode (109), a semiconductor layer (105), a gate electrode (103), and an insulating layer (104); wherein the semiconductor layer (105) contains a composite metal oxide obtained by adding to a first metal oxide an oxide having an oxygen dissociation energy that is at least 200 kJ/mol greater than the oxygen dissociation energy of the first metal oxide, whereby the amount of oxygen vacancy is controlled; and the insulating layer (104) is provided with an SiO2 layer, a high-permittivity first layer, and a high-permittivity second layer, whereby the dipoles generated at the boundary between the SiO2 layer and the high-permittivity layers are used to control the threshold voltage.
    Type: Application
    Filed: August 26, 2016
    Publication date: December 15, 2016
    Applicant: National Institute for Materials Science
    Inventors: Toshihide Nabatame, Kazuhito Tsukagoshi, Shinya Aikawa, Toyohiro Chikyo
  • Patent number: 8759925
    Abstract: To provide a method for reducing a thickness of an interfacial layer, which contains: (a) forming a film of an oxide of a first metal on a semiconductor layer via an oxide film of a semiconductor serving as an interfacial layer; and (b) forming a film of an oxide of a second metal on the film of the oxide of the first metal, where the second metal has higher valency than that of the first metal.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: June 24, 2014
    Assignee: National Institute for Materials Science
    Inventors: Naoto Umezawa, Toyohiro Chikyo, Toshihide Nabatame
  • Patent number: 8575038
    Abstract: To provide a method for reducing a thickness of an interfacial layer, which contains: (a) forming a film of an oxide of a first metal on a semiconductor layer via an oxide film of a semiconducdor serving as an interfacial layer; and (b) forming a film of an oxide of a second metal on the film of the oxide of the first metal, where the second metal has higher valency than that of the first metal.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: November 5, 2013
    Assignee: National Institute for Materials Science
    Inventors: Naoto Umezawa, Toyohiro Chikyo, Toshihide Nabatame
  • Publication number: 20120280372
    Abstract: To provide a method for reducing a thickness of an interfacial layer, which contains: (a) forming a film of an oxide of a first metal on a semiconductor layer via an oxide film of a semiconducdor serving as an interfacial layer; and (b) forming a film of an oxide of a second metal on the film of the oxide of the first metal, where the second metal has higher valency than that of the first metal.
    Type: Application
    Filed: May 29, 2012
    Publication date: November 8, 2012
    Inventors: Naoto Umezawa, Toyohiro Chikyo, Toshihide Nabatame
  • Patent number: 8207584
    Abstract: After forming a pure silicon oxide film on respective surfaces of an n-type well and a p-type well, an oxygen deficiency adjustment layer made of an oxide of 2A group elements, an oxide of 3A group elements, an oxide of 3B group elements, an oxide of 4A group elements, an oxide of 5A group elements or the like, a high dielectric constant film, and a conductive film having a reduction catalyst effect to hydrogen are sequentially deposited on the silicon oxide film, and the substrate is heat treated in the atmosphere containing H2, thereby forming a dipole between the oxygen deficiency adjustment layer and the silicon oxide film. Then, the conductive film, the high dielectric constant film, the oxygen deficiency adjustment layer, the silicon oxide film and the like are patterned, thereby forming a gate electrode and a gate insulating film.
    Type: Grant
    Filed: December 6, 2008
    Date of Patent: June 26, 2012
    Assignees: Renesas Electronics Corporation, Rohm Co., Ltd.
    Inventors: Toshihide Nabatame, Kunihiko Iwamoto, Yuuichi Kamimuta
  • Patent number: 8168547
    Abstract: The transistor characteristics of a MIS transistor provided with a gate insulating film formed to contain oxide with a relative dielectric constant higher than that of silicon oxide are improved. After a high dielectric layer made of hafnium oxide is formed on a main surface of a semiconductor substrate, the main surface of the semiconductor substrate is heat-treated in a non-oxidation atmosphere. Next, an oxygen supplying layer made of hafnium oxide deposited by ALD and having a thickness smaller than that of the high dielectric layer is formed on the high dielectric layer, and a cap layer made of tantalum nitride is formed. Thereafter, the main surface of the semiconductor substrate is heat-treated.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: May 1, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Toshihide Nabatame
  • Patent number: 7820503
    Abstract: An object of the present invention is to simplify manufacturing process of an n channel MIS transistor and a p channel MIS transistor with gate electrodes formed of a metal material. For its achievement, gate electrodes of each of the n channel MIS transistor and the p channel MIS transistor are simultaneously formed by patterning ruthenium film deposited on a gate insulator. Next, by introducing oxygen into each of the gate electrodes, the gate electrodes are transformed into those having high work function. Thereafter, by selectively reducing the gate electrode of the n channel MIS transistor, it is transformed into a gate electrode having low work function.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: October 26, 2010
    Assignees: Renesas Electronics Corporation, Tokyo Electron Limited
    Inventors: Toshihide Nabatame, Masaru Kadoshima, Hiroyuki Takaba
  • Patent number: 7790627
    Abstract: A method of manufacturing a metal compound thin film is disclosed. The method may include forming a first metal compound layer on a substrate by atomic layer deposition, performing annealing on the first metal compound layer in an atmosphere containing a nitrogen compound gas, thereby diffusing nitrogen into the first metal compound layer, and forming a second metal compound layer on the first metal compound layer by atomic layer deposition.
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: September 7, 2010
    Assignee: Rohm Co., Ltd.
    Inventors: Kunihiko Iwamoto, Toshihide Nabatame, Koji Tominaga, Tetsuji Yasuda
  • Patent number: 7772678
    Abstract: After the surface of the substrate is cleaned, an interface layer or an antidiffusion film is formed. A metal oxide film is built upon the antidiffusion film Annealing is done in an NH3 atmosphere so as to diffuse nitrogen in the metal oxide film. Building of the metal oxide film and diffusion of nitrogen are repeated several times, whereupon annealing is done in an O2 atmosphere. By annealing the film in an O2 atmosphere at a temperature higher than 650° C., the leak current in the metal oxide film is controlled.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: August 10, 2010
    Assignees: Rohm Co., Ltd., Horiba, Ltd., Renesas Technology Corp.
    Inventors: Kunihiko Iwamoto, Koji Tominaga, Toshihide Nabatame, Tomoaki Nishimura
  • Patent number: 7618855
    Abstract: A technology capable of improving the yield in a manufacturing process of a MISFET with a gate electrode formed of a metal silicide film. A gate insulating film is formed on a semiconductor substrate and silicon gate electrodes formed of a polysilicon film are formed on the gate insulating film. Then, after a silicon oxide film is formed so as to cover the silicon gate electrodes, a surface of the silicon oxide film is polished by CMP, thereby exposing the surface of the silicon gate electrodes. Subsequently, a patterned insulating film is formed on the silicon oxide film. Thereafter, an adhesion film is formed on the silicon oxide film and the insulating film. Then, a nickel film is formed on the adhesion film. Thereafter, a silicide reaction is caused to occur between the silicon gate electrode and the nickel film via the adhesion film.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: November 17, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Masaru Kadoshima, Toshihide Nabatame
  • Patent number: 7586755
    Abstract: Through an improvement of module size increase due to mounting a single passive element on a substrate and an increase in the mounting cost, to provide a highly reliable, high performance and small sized electronic circuit component which permits to integrate a variety of electronic parts such as capacitors, inductors and resistors in a high density with low cost. The electronic circuit component comprises an insulator substrate, a plurality of electrodes having different areas provided on the insulator substrate, one or more elements selected from a capacitor element of dielectric material sandwiched between the electrodes, an inductor element and resistor element, a metal wiring connecting the elements, a metal terminal part of a part of the metal wiring and an organic insulator material covering the elements and the circumference of the metal wiring portion excluding the metal terminal portion.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: September 8, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Toshiya Satoh, Masahiko Ogino, Takao Miwa, Takashi Naitou, Takashi Namekawa, Toshihide Nabatame, Shigehisa Motowaki
  • Patent number: 7511338
    Abstract: An object of the present invention is to simplify manufacturing process of an n channel MIS transistor and a p channel MIS transistor with gate electrodes formed of a metal material. For its achievement, gate electrodes of each of the n channel MIS transistor and the p channel MIS transistor are simultaneously formed by patterning ruthenium film deposited on a gate insulator. Next, by introducing oxygen into each of the gate electrodes, the gate electrodes are transformed into those having high work function. Thereafter, by selectively reducing the gate electrode of the n channel MIS transistor, it is transformed into a gate electrode having low work function.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: March 31, 2009
    Assignees: Renesas Technology Corp., Tokyo Electron Limited
    Inventors: Toshihide Nabatame, Masaru Kadoshima, Hiroyuki Takaba
  • Patent number: 7482234
    Abstract: After the surface of the substrate is cleaned, an interface layer or an antidiffusion film is formed. A metal oxide film is built upon the antidiffusion film Annealing is done in an NH3 atmosphere so as to diffuse nitrogen in the metal oxide film. Building of the metal oxide film and diffusion of nitrogen are repeated several times, whereupon annealing is done in an O2 atmosphere. By annealing the film in an O2 atmosphere at a temperature higher than 650° C., the leak current in the metal oxide film is controlled.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: January 27, 2009
    Assignees: Rohm Co., Ltd., Horiba, Ltd., Renesas Technology Corp.
    Inventors: Kunihiko Iwamoto, Koji Tominaga, Toshihide Nabatame, Tomoaki Nishimura
  • Publication number: 20080293229
    Abstract: An object of the present invention is to simplify manufacturing process of an n channel MIS transistor and a p channel MIS transistor with gate electrodes formed of a metal material. For its achievement, gate electrodes of each of the n channel MIS transistor and the p channel MIS transistor are simultaneously formed by patterning ruthenium film deposited on a gate insulator. Next, by introducing oxygen into each of the gate electrodes, the gate electrodes are transformed into those having high work function. Thereafter, by selectively reducing the gate electrode of the n channel MIS transistor, it is transformed into a gate electrode having low work function.
    Type: Application
    Filed: July 30, 2008
    Publication date: November 27, 2008
    Inventors: Toshihide Nabatame, Masaru Kadoshima, Hiroyuki Takaba
  • Publication number: 20080283929
    Abstract: In a p channel MOS transistor and an n channel MOS transistor each having a gate electrode made of metal on a gate insulating film made of oxide whose relative dielectric constant is higher than that of silicon oxide, threshold voltage thereof is reduced. A gate insulating film of a p channel MOS transistor and an n channel MOS transistor is made of hafnium oxide, a gate electrode of the p channel MOS transistor is made of ruthenium, and a gate electrode of the n channel MOS transistor is made of alloy containing ruthenium as a base material and hafnium.
    Type: Application
    Filed: May 11, 2008
    Publication date: November 20, 2008
    Inventor: Toshihide Nabatame