Abstract: A waveform observation system includes two communication nodes, a waveform observation apparatus, and a signal generation portion. The two communication nodes execute a full-duplex communication by a differential signal through a transmission line. The waveform observation apparatus observes a communication signal waveform in the transmission line in response to an input of a trigger signal. The signal generation portion outputs the trigger signal. One of the two communication nodes generates a clock signal, and transmits a signal in synchronization with the clock signal. Remaining one of the two communication nodes reproduces the clock signal included in the signal received from the one of the two communication nodes, and transmits a signal in synchronization with the clock signal that is reproduced. The signal generation portion outputs the trigger signal when equal to or more than two symbols indicated by the signal output to the transmission line consecutively coincide with one another.

Abstract: A waveform observation system includes two communication nodes, a waveform observation apparatus, and a signal generation portion. The two communication nodes execute a full-duplex communication by a differential signal through a transmission line. The waveform observation apparatus observes a communication signal waveform in the transmission line in response to an input of a trigger signal. The signal generation portion outputs the trigger signal. One of the two communication nodes generates a clock signal, and transmits a signal in synchronization with the clock signal. Remaining one of the two communication nodes reproduces the clock signal included in the signal received from the one of the two communication nodes, and transmits a signal in synchronization with the clock signal that is reproduced. The signal generation portion outputs the trigger signal when equal to or more than two symbols indicated by the signal output to the transmission line consecutively coincide with one another.

Abstract: A power line communication system includes a master side transceiver of a master communication device, a slave side transceiver of a slave communication device, a power wire, and a ground wire. The master communication device includes a voltage changeover portion changing supply voltage in steps. The master side transceiver is connected to the slave side transceiver through the power wire and the ground wire. The slave side transceiver transmits first information to the master side transceiver by a differential transmission. The voltage changeover portion changes the supply voltage so as the master side transceiver to transmit second information to the slave side transceiver. A master communication device includes a master side transceiver and a voltage changeover portion.

Abstract: A power line communication system includes a master side transceiver of a master communication device, a slave side transceiver of a slave communication device, a power wire, and a ground wire. The master communication device includes a voltage changeover portion changing supply voltage in steps. The master side transceiver is connected to the slave side transceiver through the power wire and the ground wire. The slave side transceiver transmits first information to the master side transceiver by a differential transmission. The voltage changeover portion changes the supply voltage so as the master side transceiver to transmit second information to the slave side transceiver. A master communication device includes a master side transceiver and a voltage changeover portion.

Abstract: A communication slave used in a communication network system includes a control device, a capacitive element, a voltage determining portion, and a time measuring portion. The control device controls communication with a master. The capacitive element is coupled between a high-potential side bus and a low-potential side bus. The voltage determining portion determines whether a voltage between the buses exceeds a threshold voltage. The time measuring portion measures a time from when a charge of the capacitive element through the buses is started to when the voltage determining portion determines that the voltage exceeds the threshold voltage. The control device sets an ID value for communicating with the master based on a length of the time measured by the time measuring portion.

Abstract: A synchronization signal detection apparatus includes a temporary synchronization signal detector and a final synchronization signal detector. A header of a synchronization signal has at least M successive bits of a first level, where M is an integer more than the Nth power of 2, and N is a positive integer. The synchronization signal has alternating bits starting with a second level. The temporary synchronization signal detector detects the Nth power of 2 successive bits of the first level as a temporary synchronization signal when receiving the Nth power of 2 successive bits of the first level before receiving the alternating bits. The final synchronization signal detector determines that the detected temporary synchronization signal is the header when receiving the at least M successive bits of the first level.

Abstract: In a communication network system in which a master and a plurality of communication slaves are coupled through a high-potential side bus and a low-potential side bus in a daisy-chain manner, each of the communication slaves includes a control circuit, a resistance element, and a potential difference detecting portion. The control circuit controls communication with the master. The resistance element is inserted into the high-potential side bus at a portion located downstream of a point where the control circuit is coupled with the high-potential side bus. The potential difference detecting portion detects a potential difference between an upstream terminal of the resistance element and the low-potential side bus. The control circuit sets an ID value for communicating with the master in accordance with the potential difference detected by the potential difference detecting portion.

Abstract: In a PWM communication system, a sensor unit transmits as reference pulses transmission signals, which exhibit duty cycles of 100% and 0%, respectively, prior to transmission of a transmission signal, which has data items compressed thereinto by a signal processing circuit. An input capture circuit of an ECU measures the duty time and the PWM cycle of the transmission signal according to a timer clock of a timer circuit. A signal processing circuit of the ECU produces a duty cycle correction factor k based on the measured duty times and PWM cycles of the reference pulses, produces receiving data based on the duty time and the PWM cycle of the transmission signal, and the duty cycle correction factor, and separates the receiving data into sensor output values of a pressure sensor and a temperature sensor.

Abstract: In a communication system, plural nodes are communicably connected to a communication line and mutually communicate based on an NRZ (Non Return to Zero) code. Each node detects, as a data frame head, a dominant level when a signal on the line changes to a dominant level during a stand-by state of the line. An activation frame is transmitted during a sleep mode. The activation frame has an activation pattern area storing therein a bit pattern showing that the frame is the activation frame, a specific pattern area storing therein a bit pattern showing a node to be activated, a boundary position satisfying a predetermined boundary condition and being a boundary between the activation and specific pattern areas. Each node performs a switchover from the sleep mode to a normal mode based on the bit patterns in the activation and specific pattern areas and information given by the boundary position.

Abstract: A data reception apparatus includes: an oscillation circuit that multiplies or divides an oscillation signal from a CR oscillator based on a cycle setting value, and outputs a clock signal corresponding to the multiplied or divided oscillation signal; a temperature detector; a memory; a clock cycle setting element that reads the cycle setting value corresponding to the temperature from the memory, and inputs the cycle setting value into the oscillation circuit; a receiver that receives a data signal defined by the clock signal; a measurement element that measures a unit bit length of the data signal by counting the clock signal; and a correction element that corrects the cycle setting value based on a count value of the clock signal and a reference count value of a reference cycle corresponding to the unit bit length, and rewrites the cycle setting value with the corrected cycle setting value.

Abstract: In a PWM communication system, a sensor unit transmits as reference pulses transmission signals, which exhibit duty cycles of 100% and 0%, respectively, prior to transmission of a transmission signal, which has data items compressed thereinto by a signal processing circuit. An input capture circuit of an ECU measures the duty time and the PWM cycle of the transmission signal according to a timer clock of a timer circuit. A signal processing circuit of the ECU produces a duty cycle correction factor k based on the measured duty times and PWM cycles of the reference pulses, produces receiving data based on the duty time and the PWM cycle of the transmission signal, and the duty cycle correction factor, and separates the receiving data into sensor output values of a pressure sensor and a temperature sensor.

Abstract: A communication slave used in a communication network system includes a control device, a capacitive element, a voltage determining portion, and a time measuring portion. The control device controls communication with a master. The capacitive element is coupled between a high-potential side bus and a low-potential side bus. The voltage determining portion determines whether a voltage between the buses exceeds a threshold voltage. The time measuring portion measures a time from when a charge of the capacitive element through the buses is started to when the voltage determining portion determines that the voltage exceeds the threshold voltage. The control device sets an ID value for communicating with the master based on a length of the time measured by the time measuring portion.

Abstract: A synchronization signal detection apparatus includes a temporary synchronization signal detector and a final synchronization signal detector. A header of a synchronization signal has at least M successive bits of a first level, where M is an integer more than the Nth power of 2, and N is a positive integer. The synchronization signal has alternating bits starting with a second level. The temporary synchronization signal detector detects the Nth power of 2 successive bits of the first level as a temporary synchronization signal when receiving the Nth power of 2 successive bits of the first level before receiving the alternating bits. The final synchronization signal detector determines that the detected temporary synchronization signal is the header when receiving the at least M successive bits of the first level.

Abstract: In a communication network system in which a master and a plurality of communication slaves are coupled through a high-potential side bus and a low-potential side bus in a daisy-chain manner, each of the communication slaves includes a control circuit, a resistance element, and a potential difference detecting portion. The control circuit controls communication with the master. The resistance element is inserted into the high-potential side bus at a portion located downstream of a point where the control circuit is coupled with the high-potential side bus. The potential difference detecting portion detects a potential difference between an upstream terminal of the resistance element and the low-potential side bus. The control circuit sets an ID value for communicating with the master in accordance with the potential difference detected by the potential difference detecting portion.

Abstract: A communication system includes: a master; a plurality of slaves; and a bus for coupling among the master and the plurality of slaves in order to communicate asynchronously among the master and the plurality of slaves. The master supplies electricity to the bus in a power supply period. The master or the slave drives the bus for transmitting a one-bit data through the bus in a data transmission period. The power supply period and the data transmission period are successively performed so that data communication provided by a plurality of one-bit periods is performed among the master and the plurality of slaves. The master finely changes a communication frequency in the data communication. The master changes a drive level of the bus within a predetermined acceptable range in the data communication.

Abstract: A semiconductor integrated circuit having a test circuit for collecting test data at any time based on interaction with an external source is provided. A communication circuit receives a data frame that is transferred to a data buffer. Data portions are transferred to a test unit of a test circuit. A counter starts a count operation based on a system clock when count information is transferred. If one of the data portions indicates the transferred data is test data, and another portion indicates a data collection specification command, the test unit outputs decoded address data to interact with a circuit-under-test when the counter completes the count operation based on another portion of the frame. A data buffer is supplied with the address data to facilitate storage of the data transferred from the circuit-under-test.

Abstract: A microcomputer for functioning according to operation modes includes; a mode counter that counts the number of times of level change in a signal applied to a mode setting terminal; a mode decoder that decodes output data of the mode counter to output a mode signal, which represents one operation mode; a clock input terminal; a data terminal through which serial data is inputted synchronously with a serial clock signal applied to the clock input terminal; a serial-to-parallel conversion unit that converts the serial data into parallel data and stores the parallel data in an input data buffer; and a switching means that switches to a state that a CPU can access to the input data buffer in a test mode. In the test mode, test instruction data is capable of being inputted from an external circuit.

Abstract: A microcomputer includes a CPU capable of performing a plurality of tasks in a parallel time-sharing operation. The tasks include at least one special task having a fixed loop program with a constant increase of an instruction address. When the CPU performs a conditional judgment instruction in the special task, the CPU prohibits reflecting an execution result of the conditional judgment instruction to both of the CPU and a periphery circuit in a case where it is no need to perform an instruction described in the special task after the conditional judgment instruction.

Abstract: A communication system includes: a master; a plurality of slaves; and a bus for coupling among the master and the plurality of slaves in order to communicate asynchronously among the master and the plurality of slaves. The master supplies electricity to the bus in a power supply period. The master or the slave drives the bus for transmitting a one-bit data through the bus in a data transmission period. The power supply period and the data transmission period are successively performed so that data communication provided by a plurality of one-bit periods is performed among the master and the plurality of slaves. The master finely changes a communication frequency in the data communication. The master changes a drive level of the bus within a predetermined acceptable range in the data communication.

Abstract: When each slave ECU is powered on and activated while connected to a communication network through a harness, it reads out divided voltage potential applied by voltage dividing resistors in each ID determining signal line, and allows reception of a data packet transmitted from control ECU when a wait time corresponding to the divided voltage potential elapses. The control ECU successively transmits a data packet containing as a main body ID data to be allocated to each slave ECU, and each slave ECU sets ID data transmitted as its own ID.