Abstract: During software development, a multichip module is used which encloses a target chip and a development chip in one package. A CPU of the development chip fetches instructions from a flash memory in the chip to execute them, and accesses RAM and peripheral circuits in the chip. For motor control circuits that exist only in the target chip, the CPU accesses them via serial communication. When the one-chip microcomputer operates alone, its CPU switches a switching circuit to a JTAG interface side to actuate a motor control circuit via internal serial communication.

Abstract: In a power supply circuit, when switches are turned off, current flows from a battery power supply line through resistors, input terminals, diodes and a terminal and further from a terminal into IC. When a microcomputer operates in a low power consumption operating mode, the power supply voltage is higher than a target voltage, and a control voltage output from an operational amplifier increases, so that a transistor is turned off. At this time, a current sink circuit operates and a transistor is turned on, so that excessive current flows into the current sink circuit to suppress increase of the power supply voltage.

Abstract: In a microcomputer, a watch-dog timer and a sleep control timer share a counter in their signal generating circuits. In a normal operation mode, an AND gate is in a signal passing state and a reset signal RST can be outputted. In a sleep mode, another AND gate is in a signal passing state and a wake-up signal WKUP can be outputted.

Abstract: The present invention relates to a clock control circuit apparatus including a first oscillation circuit for generating a first clock signal and a second oscillation circuit for generating a second clock signal and capable of, when the two clock signals are put to use, improving the reliability of oscillation operations thereof. In the clock control circuit apparatus, a sub-clock correction unit corrects an oscillation frequency of a sub-clock signal on the basis of a main clock signal, while a main clock monitoring unit monitors an oscillation state of the main clock signal on the basis of the sub-clock signal.

Abstract: A first receiving message is stored in a message box and a CPU reads the first receiving message from the message box. Meanwhile, a second receiving message is once stored in the message box and thereafter transferred directly to a RAM by a DMA controller. The number of times of transfer operation is restricted with an upper limit value. The CPU does not read the second receiving message from the message box but from the RAM and executes the processes based on the message. Generation of failure in the receiving data fetching processes is reduced without physical expansion of the storage regions of the message box.

Abstract: A first receiving message is stored into a message box and a CPU reads the first receiving message from the message box. Meanwhile, a second receiving message is once stored in the message box and thereafter transferred in direct to a RAM by a DMA controller. The number of times of transfer operation is restricted with an upper limit value. The CPU does not read the second receiving message from the message box but from the RAM and executes the processes based on the message. Generation of failure in the receiving data fetching processes is reduced without physical expansion of the storage regions of the message box.