Patents by Inventor Toshihiko Matsuoka
Toshihiko Matsuoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7631212Abstract: A communication system includes: a master; a plurality of slaves; and a bus for coupling among the master and the plurality of slaves in order to communicate asynchronously among the master and the plurality of slaves. The master supplies electricity to the bus in a power supply period. The master or the slave drives the bus for transmitting a one-bit data through the bus in a data transmission period. The power supply period and the data transmission period are successively performed so that data communication provided by a plurality of one-bit periods is performed among the master and the plurality of slaves. The master finely changes a communication frequency in the data communication. The master changes a drive level of the bus within a predetermined acceptable range in the data communication.Type: GrantFiled: March 20, 2007Date of Patent: December 8, 2009Assignee: DENSO CORPORATIONInventors: Katsutoyo Misawa, Masato Rinnai, Toshihiko Matsuoka, Hideaki Ishihara
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Patent number: 7554415Abstract: A microcomputer includes an oscillator for generating a clock signal having a frequency by using a CR circuit, a multiplier for outputting the clock signal having a multiplied frequency relative to the frequency generated by the oscillator based on data from an external source, a temperature detection unit for detecting temperature at a proximity of the CR circuit, a storage unit for storing data that enables the multiplied frequency of the clock signal in an output from the multiplier to have a constant value based on a temperature-dependent oscillation characteristic of the oscillator, and a control unit for setting a multiplication value for generating the multiplied frequency of the clock signal to the multiplier based on the data in the storage unit that is correlated to the temperature detected by the temperature detection unit.Type: GrantFiled: December 19, 2006Date of Patent: June 30, 2009Assignee: DENSO CORPORATIONInventors: Toshihiko Matsuoka, Hideaki Ishihara
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Publication number: 20090096504Abstract: A data reception apparatus includes: an oscillation circuit that multiplies or divides an oscillation signal from a CR oscillator based on a cycle setting value, and outputs a clock signal corresponding to the multiplied or divided oscillation signal; a temperature detector; a memory; a clock cycle setting element that reads the cycle setting value corresponding to the temperature from the memory, and inputs the cycle setting value into the oscillation circuit; a receiver that receives a data signal defined by the clock signal; a measurement element that measures a unit bit length of the data signal by counting the clock signal; and a correction element that corrects the cycle setting value based on a count value of the clock signal and a reference count value of a reference cycle corresponding to the unit bit length, and rewrites the cycle setting value with the corrected cycle setting value.Type: ApplicationFiled: October 9, 2008Publication date: April 16, 2009Applicant: DENSO CORPORATIONInventors: Kazushi Matsuo, Toshihiko Matsuoka, Hideaki Ishihara
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Patent number: 7519753Abstract: A communication system includes a master control unit, a plurality of slave control units, and buses connecting the master control unit and the slave control units for the asynchronous communication. When the master control unit starts the communication, each slave control unit transmits a plurality of data bits represented by whether the buses be driven to the master control unit in data transmission periods assigned to the slave control units based on a start of communication, and the master control unit drives the buses to insert a period for supplying power while data bits are being transmitted in the data transmission period. The slave control unit provides a non-driving period, which stops driving the buses, at an end of the data bit transmission period.Type: GrantFiled: September 12, 2006Date of Patent: April 14, 2009Assignee: DENSO CORPORATIONInventors: Katsutoyo Misawa, Masato Rinnai, Toshihiko Matsuoka, Yoshinori Teshima, Hideaki Ishihara
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Publication number: 20090009211Abstract: A microcomputer for functioning according to operation modes includes: a mode counter that counts the number of times of level change in a signal applied to a mode setting terminal; a mode decoder that decodes output data of the mode counter to output a mode signal, which represents one operation mode; a clock input terminal; a data terminal through which serial data is inputted synchronously with a serial clock signal applied to the clock input terminal; a serial-to-parallel conversion unit that converts the serial data into parallel data and stores the parallel data in an input data buffer; and a switching means that switches to a state that a CPU can access to the input data buffer in a test mode. In the test mode, test instruction data is capable of being inputted from an external circuit.Type: ApplicationFiled: May 29, 2008Publication date: January 8, 2009Applicant: DENSO CORPORATIONInventors: Naoki Ito, Hideaki Ishihara, Toshihiko Matsuoka, Katsutoyo Misawa
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Patent number: 7467294Abstract: A microcomputer includes a plurality of operation mode selecting terminals to which data for selecting plural operation modes are set. The plurality of operation mode selecting terminals is designed so as to be usable as general-purpose input terminals or output terminals. A decoder decodes the data set to the plurality of operation mode selecting terminals and outputting a mode signal for switching an internal function in accordance with a selected operation mode. A timing signal output unit outputs to the decoder a timing signal for making the decoder execute a decode operation. The timing signal output unit outputs the timing signal when at least one of power-on-reset and an externally controlled reset is varied from an active state to an inactive state.Type: GrantFiled: November 10, 2005Date of Patent: December 16, 2008Assignee: DENSO CORPORATIONInventors: Toshihiko Matsuoka, Naoki Ito, Hideaki Ishihara, Yasuyuki Ishikawa
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Patent number: 7444529Abstract: A CPU, when shifting to a sleep mode, discontinues the oscillating operations of an oscillation circuit and of a frequency multiplier circuit through a low power consumption control circuit. A flash power source circuit discontinues the oscillating operations of the circuits or interrupts or resumes the supply of an external power source in response to resumption of the halted operation. When the CPU is to be shifted to the sleep mode, the frequency multiplier circuit holds the set oscillation control conditions. When the oscillating operation is to be resumed, operates based on the oscillation control conditions that are held. When the sleep mode is reset, the CPU makes access to the mask ROM and immediately reads out a control program that is to be executed right after the wakeup.Type: GrantFiled: September 29, 2005Date of Patent: October 28, 2008Assignee: DENSO CORPORATIONInventors: Toshihiko Matsuoka, Hideaki Ishihara, Yukari Sugiura
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Patent number: 7421384Abstract: During software development, a multichip module is used which encloses a target chip and a development chip in one package. A CPU of the development chip fetches instructions from a flash memory in the chip to execute them, and accesses RAM and peripheral circuits in the chip. For motor control circuits that exist only in the target chip, the CPU accesses them via serial communication. When the one-chip microcomputer operates alone, its CPU switches a switching circuit to a JTAG interface side to actuate a motor control circuit via internal serial communication.Type: GrantFiled: December 2, 2004Date of Patent: September 2, 2008Assignee: DENSO CORPORATIONInventors: Kenji Yamada, Hideaki Ishihara, Kyouichi Suzuki, Yoshinori Teshima, Toshihiko Matsuoka, Naoki Ito
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Publication number: 20080183416Abstract: A semiconductor integrated circuit having a test circuit for collecting test data at any time based on interaction with an external source is provided. A communication circuit receives a data frame that is transferred to a data buffer. Data portions are transferred to a test unit of a test circuit. A counter starts a count operation based on a system clock when count information is transferred. If one of the data portions indicates the transferred data is test data, and another portion indicates a data collection specification command, the test unit outputs decoded address data to interact with a circuit-under-test when the counter completes the count operation based on another portion of the frame. A data buffer is supplied with the address data to facilitate storage of the data transferred from the circuit-under-test.Type: ApplicationFiled: January 29, 2008Publication date: July 31, 2008Applicant: DENSO CORPORATIONInventor: Toshihiko Matsuoka
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Patent number: 7356719Abstract: In an EEPROM of a microcomputer, data is stored for determining a communication rate CMR for fixing the data transmission time of one frame managed by a communication circuit on the basis of an oscillation output characteristic of a CR oscillating circuit that varies in accordance with temperature. CPU reads out data stored in EEPROM in accordance with the temperature detected by a temperature detecting circuit, and sets the determined communication CMR into the communication circuit.Type: GrantFiled: February 21, 2006Date of Patent: April 8, 2008Assignee: DENSO CORPORATIONInventors: Toshihiko Matsuoka, Hideaki Ishihara, Yukari Sugiura
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Publication number: 20070233920Abstract: A communication system includes: a master; a plurality of slaves; and a bus for coupling among the master and the plurality of slaves in order to communicate asynchronously among the master and the plurality of slaves. The master supplies electricity to the bus in a power supply period. The master or the slave drives the bus for transmitting a one-bit data through the bus in a data transmission period. The power supply period and the data transmission period are successively performed so that data communication provided by a plurality of one-bit periods is performed among the master and the plurality of slaves. The master finely changes a communication frequency in the data communication. The master changes a drive level of the bus within a predetermined acceptable range in the data communication.Type: ApplicationFiled: March 20, 2007Publication date: October 4, 2007Applicant: DENSO CORPORATIONInventors: Katsutoyo Misawa, Masato Rinnai, Toshihiko Matsuoka, Hideaki Ishihara
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Publication number: 20070164832Abstract: A microcomputer includes an oscillator for generating a clock signal having a frequency by using a CR circuit, a multiplier for outputting the clock signal having a multiplied frequency relative to the frequency generated by the oscillator based on data from an external source, a temperature detection unit for detecting temperature at a proximity of the CR circuit, a storage unit for storing data that enables the multiplied frequency of the clock signal in an output from the multiplier to have a constant value based on a temperature-dependent oscillation characteristic of the oscillator, and a control unit for setting a multiplication value for generating the multiplied frequency of the clock signal to the multiplier based on the data in the storage unit that is correlated to the temperature detected by the temperature detection unit.Type: ApplicationFiled: December 19, 2006Publication date: July 19, 2007Applicant: DENSO CORPORATIONInventors: Toshihiko Matsuoka, Hideaki Ishihara
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Patent number: 7216250Abstract: The present invention relates to a clock control circuit apparatus including a first oscillation circuit for generating a first clock signal and a second oscillation circuit for generating a second clock signal and capable of, when the two clock signals are put to use, improving the reliability of oscillation operations thereof. In the clock control circuit apparatus, a sub-clock correction unit corrects an oscillation frequency of a sub-clock signal on the basis of a main clock signal, while a main clock monitoring unit monitors an oscillation state of the main clock signal on the basis of the sub-clock signal.Type: GrantFiled: December 23, 2003Date of Patent: May 8, 2007Assignee: DENSO CorporationInventors: Toshihiko Matsuoka, Yoshinori Teshima, Shinichi Noda, Susumu Tsuruta, Hiroshi Fujii, Hideaki Ishihara
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Publication number: 20070083686Abstract: A communication system includes a master control unit, a plurality of slave control units, and buses connecting the master control unit and the slave control units for the asynchronous communication. When the master control unit starts the communication, each slave control unit transmits a plurality of data bits represented by whether the buses be driven to the master control unit in data transmission periods assigned to the slave control units based on a start of communication, and the master control unit drives the buses to insert a period for supplying power while data bits are being transmitted in the data transmission period. The slave control unit provides a non-driving period, which stops driving the buses, at an end of the data bit transmission period.Type: ApplicationFiled: September 12, 2006Publication date: April 12, 2007Applicant: DENSO CORPORATIONInventors: Katsutoyo Misawa, Masato Rinnai, Toshihiko Matsuoka, Yoshinori Teshima, Hideaki Ishihara
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Patent number: 7149915Abstract: In a microcomputer, a watch-dog timer and a sleep control timer share a counter in their signal generating circuits. In a normal operation mode, an AND gate is in a signal passing state and a reset signal RST can be outputted. In a sleep mode, another AND gate is in a signal passing state and a wake-up signal WKUP can be outputted.Type: GrantFiled: February 24, 2004Date of Patent: December 12, 2006Assignee: Denso CorporationInventors: Toshihiko Matsuoka, Yukari Ishiguro, Hideaki Ishihara
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Publication number: 20060195711Abstract: In an EEPROM of a microcomputer, data is stored for determining a communication rate CMR for fixing the data transmission time of one frame managed by a communication circuit on the basis of an oscillation output characteristic of a CR oscillating circuit that varies in accordance with temperature. CPU reads out data stored in EEPROM in accordance with the temperature detected by a temperature detecting circuit, and sets the determined communication CMR into the communication circuit.Type: ApplicationFiled: February 21, 2006Publication date: August 31, 2006Applicant: DENSO CORPORATIONInventors: Toshihiko Matsuoka, Hideaki Ishihara, Yukari Sugiura
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Publication number: 20060155976Abstract: A microcomputer includes a CPU capable of performing a plurality of tasks in a parallel time-sharing operation. The tasks include at least one special task having a fixed loop program with a constant increase of an instruction address. When the CPU performs a conditional judgement instruction in the special task, the CPU prohibits reflecting an execution result of the conditional judgement instruction to both of the CPU and a periphery circuit in a case where it is no need to perform an instruction described in the special task after the conditional judgement instruction.Type: ApplicationFiled: December 21, 2005Publication date: July 13, 2006Applicant: DENSO CORPORATIONInventors: Naoki Ito, Masahiro Kamiya, Hideaki Ishihara, Akimasa Niwa, Takayuki Matsuda, Toshihiko Matsuoka
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Publication number: 20060107082Abstract: A microcomputer includes a plurality of operation mode selecting terminals to which data for selecting plural operation modes are set. The plurality of operation mode selecting terminals is designed so as to be usable as general-purpose input terminals or output terminals. A decoder decodes the data set to the plurality of operation mode selecting terminals and outputting a mode signal for switching an internal function in accordance with a selected operation mode. A timing signal output unit outputs to the decoder a timing signal for making the decoder execute a decode operation. The timing signal output unit outputs the timing signal when at least one of power-on-reset and an externally controlled reset is varied from an active state to an inactive state.Type: ApplicationFiled: November 10, 2005Publication date: May 18, 2006Applicant: c/o DENSO CORPORATIONInventors: Toshihiko Matsuoka, Naoki Ito, Hideaki Ishihara, Yasuyuki Ishikawa
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Publication number: 20060069933Abstract: A CPU, when shifting to a sleep mode, discontinues the oscillating operations of an oscillation circuit and of a frequency multiplier circuit through a low power consumption control circuit. A flash power source circuit discontinues the oscillating operations of the circuits or interrupts or resumes the supply of an external power source in response to resumption of the halted operation. When the CPU is to be shifted to the sleep mode, the frequency multiplier circuit holds the set oscillation control conditions. When the oscillating operation is to be resumed, operates based on the oscillation control conditions that are held. When the sleep mode is reset, the CPU makes access to the mask ROM and immediately reads out a control program that is to be executed right after the wakeup.Type: ApplicationFiled: September 29, 2005Publication date: March 30, 2006Applicant: DENSO CORPORATIONInventors: Toshihiko Matsuoka, Hideaki Ishihara, Yukari Sugiura
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Publication number: 20050152388Abstract: When each slave ECU is powered on and activated while connected to a communication network through a harness, it reads out divided voltage potential applied by voltage dividing resistors in each ID determining signal line, and allows reception of a data packet transmitted from control ECU when a wait time corresponding to the divided voltage potential elapses. The control ECU successively transmits a data packet containing as a main body ID data to be allocated to each slave ECU, and each slave ECU sets ID data transmitted as its own ID.Type: ApplicationFiled: December 7, 2004Publication date: July 14, 2005Inventors: Yukari Ishiguro, Hideaki Ishihara, Toshihiko Matsuoka