Abstract: An optical transmitter includes: a driving circuit that includes drivers each corresponding to a configuration bit of an input electrical data sequence; a MZ optical modulator that includes a first phase shifter provided in an arm and a second phase shifter provided in an arm; first capacitance elements that are electrically connected between the driving unit and the first phase shifter, each include an electric capacity weighted in response to a bit number of the configuration bit, and generate a first multilevel signal to be supplied to the first phase shifter; and second capacitance elements that are electrically connected between the driving circuit and the second phase shifter, each include an electric capacity weighted in response to a bit number of the configuration bit, and generate a second multilevel signal to be supplied to the second phase shifter.

Abstract: A frequency characteristic adjustment circuit is disclosed. The frequency characteristic adjustment circuit is disposed between an optical circuit element and a drive circuit for driving the optical circuit element. A capacitor is connected to an output of the drive circuit. A current supply circuit is controlled by a voltage generated by the drive circuit. The current supply circuit supplies a different current value depending on a voltage received from the drive circuit to the optical circuit element.

Abstract: Disclosed is a frequency characteristic adjusting circuit disposed between an optical circuit element and a drive circuit driving the optical circuit element. The frequency characteristic adjusting circuit includes a capacitor, and two or more series circuits having a resistor and a switch, the two or more series circuits being connected in parallel with the capacitor, where resistance with respect to the switch that is turned on is changed according to an output voltage of the drive circuit by changing ON or OFF of the switch such that electric charge at a contact point between the optical circuit element and the capacitor is adjusted to be constant regardless of the output voltage of the drive circuit.

Abstract: A safety level indication arrangement for a motor vehicle includes a first camera capturing first images of an environment surrounding the motor vehicle. A second camera captures second images of a driver of the motor vehicle. A microphone is associated with the passenger compartment and produces a microphone signal dependent upon sounds within the passenger compartment. At least one vehicle sensor detects an operational parameter of the motor vehicle. A display device is associated with the passenger compartment. A loudspeaker is associated with the passenger compartment. An electronic processor ascertains a safety level based on the first images and the operational parameter of the motor vehicle. The electronic processor determines how to present the ascertained safety level to the driver by use of the display device and/or the loudspeaker. The determining is dependent upon the second images and the microphone signal.

Abstract: An electronic device includes: an integrated circuit including a first power source terminal to which a first voltage is supplied from a DC power source, a second power source terminal to which a second voltage is supplied from the DC power source, a third power source terminal coupled to the first power source terminal through an internal resistance, and a fourth power source terminal coupled to the second power source terminal; and a power source circuit including a first power source line that supplies the first voltage to the first power source terminal from the DC power source, a second power source line that supplies the second voltage to the second power source terminal from the DC power source, and a bypass capacitor coupled between the third power source terminal and the fourth power source terminal.

Abstract: A vehicle includes a user interface having a plurality of components. A global positioning system determines a geographical location of the vehicle. An electronic processor is communicatively coupled to the user interface and the global positioning system. The electronic processor wirelessly receives data regarding road and traffic conditions from an external source. The electronic processor also determines which of the user interface components to use to present entertainment content to a driver of the vehicle based on the data regarding road and traffic conditions and the geographical location of the vehicle.

Abstract: A manufacturing method of a package bag (10) according to the present invention includes: a cured portion forming step of forming a cured portion (15a, 15b) on at least one side of a forming position of a rib (14) by crystallizing at least a portion of a resin constituting a film (11) by heating and cooling the film (11); and a rib forming step of forming a rib (14) by pressing the film (11) using concave and convex molds. According to the present invention, it is possible to maintain an opening state of a spout (12). Further, since additional material is not required, it is possible to suppress increase in the thickness of the package bag (10) and to reduce the bulkiness of the package bags.

Abstract: A decision feedback equalizer for N-level amplitude modulated signal, includes: (N?1) level conversion circuits to add (N?1) shifting voltages to the amplitude modulated signal respectively; (N?1)×N determination feedback equalization-correction circuits to perform N types of decision feedback equalization processing, each of which adding each of N-level offset voltages corresponded to any one of N levels of a reception data ahead of one data cycle, on each of the (N?1) level shifted signals to generate (N?1) sets of N equalization correction signals; (N?1)×N comparison circuits; (N?1)×N first latch circuits; (N?1) selection circuits to select a comparison result of the N comparison circuits in each (N?1) sets; (N?1) second latch circuits; and a decoder, wherein each of the (N?1) selection circuits selects an equalization-correction signal among the N equalization-correction signals in each (N?1) set according to outputs latched by the (N?1) second latch circuits.

Abstract: A phase interpolator has: a mixer configured to synthesize phases of a plurality of input cosine-wave or sine-wave signals whose phases are different from each other; and a bias generator configured to output a bias signal in accordance with a phase control signal to the mixer, and the mixer outputs a signal with a phase in accordance with the phase control signal.

Abstract: A decision feedback equalizer for N-level amplitude modulated signal, includes: (N-1) level conversion circuits to add (N-1) shifting voltages to the amplitude modulated signal respectively; (N-1)×N determination feedback equalization-correction circuits to perform N types of decision feedback equalization processing, each of which adding each of N-level offset voltages corresponded to any one of N levels of a reception data ahead of one data cycle, on each of the (N-1) level shifted signals to generate (N-1) sets of N equalization correction signals; (N-1)×N comparison circuits; (N-1)×N first latch circuits; (N-1) selection circuits to select a comparison result of the N comparison circuits in each (N-1) sets; (N-1) second latch circuits; and a decoder, wherein each of the (N-1) selection circuits selects an equalization-correction signal among the N equalization-correction signals in each (N-1) set according to outputs latched by the (N-1) second latch circuits.

Abstract: A clock control circuit includes: a first buffer that receives a first pair of input clocks of multi-phase clocks, buffers and outputs the first pair of input clocks; a second buffer that receives a second pair of input clocks of the multi-phase clocks, and is controllable to buffer and output the second pair of input clocks or to output a fixed level; and a frequency multiplier that performs a logical operation on an output of the first buffer and an output of the second buffer, and outputs a first pair of output clocks or a second pair of output clocks as an output clocks, the first pair of output clocks is based on a frequency which is obtained by multiplying frequencies of the multi-phase clocks, and the second pair of output clocks is based on the same frequencies as the multi-phase clocks.

Abstract: A DC-DC converter includes: a high-side switch; a low-side switch coupled to the high-side switch in series; a capacitor configured to be charged while the low-side switch is turned on and to increase a driving voltage for turning on the high-side switch by a charged voltage; a buffer configured to output a control signal for controlling the high-side switch; a latch configured to receive the control signal at a first input terminal, retain the control signal, and output the control signal to the high-side switch; and a switch configured to receive the control signal from the latch and deactivate the buffer.

Abstract: A phase interpolator has: a mixer configured to synthesize phases of a plurality of input cosine-wave or sine-wave signals whose phases are different from each other; and a bias generator configured to output a bias signal in accordance with a phase control signal to the mixer, and the mixer outputs a signal with a phase in accordance with the phase control signal.

Abstract: A clock control circuit includes: a first buffer that receives a first pair of input clocks of multi-phase clocks, buffers and outputs the first pair of input clocks; a second buffer that receives a second pair of input clocks of the multi-phase clocks, and is controllable to buffer and output the second pair of input clocks or to output a fixed level; and a frequency multiplier that performs a logical operation on an output of the first buffer and an output of the second buffer, and outputs a first pair of output clocks or a second pair of output clocks as an output clocks, the first pair of output clocks is based on a frequency which is obtained by multiplying frequencies of the multi-phase clocks, and the second pair of output clocks is based on the same frequencies as the multi-phase clocks.

Abstract: A spout member including a base portion which is fixed to a bag body, a cylindrical portion which protrudes upward from the base portion, and a sealing portion which seals a front end of the cylindrical portion through a breakable thin portion is disposed between two sheets of film forming the bag body. A sealing chamber accommodating the cylindrical portion and the sealing portion is opened by tearing the two sheets of film along an opening assisting line. An opening assisting plate protruding to at least one of a left side and a right side of the sealing portion is disposed above the opening assisting line. A sandwiching reinforcement seal portion for reinforcing the two sheets of film by sealing inner surfaces thereof is provided between the opening assisting plate and the opening assisting line.

Abstract: A DC-DC converter includes: a high-side switch; a low-side switch coupled to the high-side switch in series; a capacitor configured to be charged while the low-side switch is turned on and to increase a driving voltage for turning on the high-side switch by a charged voltage; a buffer configured to output a control signal for controlling the high-side switch; a latch configured to receive the control signal at a first input terminal, retain the control signal, and output the control signal to the high-side switch; and a switch configured to receive the control signal from the latch and deactivate the buffer.

Abstract: A manufacturing method of a package bag (10) according to the present invention includes: a cured portion forming step of forming a cured portion (15a, 15b) on at least one side of a forming position of a rib (14) by crystallizing at least a portion of a resin constituting a film (11) by heating and cooling the film (11); and a rib forming step of forming a rib (14) by pressing the film (11) using concave and convex molds. According to the present invention, it is possible to maintain an opening state of a spout (12). Further, since additional material is not required, it is possible to suppress increase in the thickness of the package bag (10) and to reduce the bulkiness of the package bags.

Abstract: A level converter circuit is provided for converting an input signal of a digital signal having a first signal level into an output signal having a second signal level higher than the first signal level. An amplifier circuit amplifies the input signal and outputs an amplified output signal, and a current generator circuit generates a control current corresponding to an operating current flowing through the amplifier circuit upon change of the signal level of the input signal. A current detector circuit detects the generated control current, and controls the operating current of the amplifier circuit to correspond to the detected control current. The current generator circuit includes series-connected first and second nMOS transistors as inserted between the current detector circuit and the ground. The first nMOS transistor operates responsive to the input signal, and the second nMOS transistor operates responsive to an inverted signal of the input signal.

Abstract: An ESD protection circuit including a first electrostatic discharge protection circuit provided between first power supply wiring and first ground wiring; a second ESD protection circuit provided between second power supply wiring and second ground wiring; a third ESD protection circuit provided between the first ground wiring and the second ground wiring; a PMOS transistor coupled to the first power supply wiring and provided between a first CMOS circuit coupled to the first ground wiring and the first power supply wiring, the first CMOS circuit receiving a signal from a first internal circuit and outputting a signal to a first node; an NMOS transistor provided between the first node and the first ground wiring; and an ESD detection circuit that renders the PMOS transistor conductive and the NMOS transistor non-conductive during normal operation, and renders the PMOS transistor non-conductive and the NMOS transistor conductive when an ESD is applied.

Abstract: A frequency synthesizer includes a voltage-controlled oscillator, a frequency range tuning circuit which detects a frequency control code that sets a voltage-controlled frequency range of the voltage-controlled oscillator corresponding to the frequency division ratio which is variably-set, and a frequency control code memory which stores the frequency control code detected by the frequency range tuning circuit corresponding to the frequency division ratio. In an initialization interval, the frequency range tuning circuit detects the frequency control code corresponding to the frequency division ratio which is variably-set, and the frequency control code memory stores the frequency control code which is detected. In a normal operation interval, in response to the frequency selection signal, the frequency control code, which is stored in the frequency control code memory and corresponds to the frequency division ratio which is variably-set, is output to the voltage-controlled oscillator.