Abstract: A semiconductor memory device which can reduce a power consumption by reducing a charging and discharging current for a gate capacity of a transistor used for pulling up a bit line which constitutes a write recovery circuit. A pair of first and second bit lines are connected to a memory cell. A potential of one of the first and second bit lines is decreased during a write cycle in accordance with write data. A first loading element is connected between a power source line and the first bit line. The power source line supplies a positive power source voltage. A second loading element is connected between the power source line and the second bit line. A first transistor is provided for pulling up the first bit line. The first transistor has a current input terminal connected to the power source line and a current output terminal connected to the first bit line. A second transistor is provided for pulling up the second bit line.

Abstract: A semiconductor memory device which can reduce a power consumption by reducing a charging and discharging current for a gate capacity of a transistor used for pulling up a bit line which constitutes a write recovery circuit. A pair of first and second bit lines are connected to a memory cell. A potential of one of the first and second bit lines is decreased during a write cycle in accordance with write data. A first loading element is connected between a power source line and the first bit line. The power source line supplies a positive power source voltage. A second loading element is connected between the power source line and the second bit line. A first transistor is provided for pulling up the first bit line. The first transistor has a current input terminal connected to the power source line and a current output terminal connected to the first bit line. A second transistor is provided for pulling up the second bit line.

Abstract: A resin part such as an instrument panel, a console box or door trim has a substrate body made of hard resin and a skin mounted on a surface of the substrate. To produce the resin part, a preformed elastic sheet is set within a mold cavity. Then, a molten resin is injected into the cavity through gates. The molten resin is first injected into the cavity through gates that are opposed to the skin and after the passage of a predetermined time, the resin is injected through gates that are not opposed to the skin, thereby forming a substrate that has the skin thermally fused to a surface thereof.

Abstract: A semiconductor integrated circuit device including: an off-substrate having a semiconductor surface with a plurality of steps each having a height of one monolayer and extending in one direction; a wiring layer formed on the semiconductor surface of the off-substrate and made of semiconductor material, the wiring layer including a plurality of conductive stripe regions and high resistance strip regions disposed in a stripe pattern, each stripe region extending in a direction parallel with the steps, and the conductive stripe regions and the high resistance stripe regions both having lattice structures identical to those of underlying surfaces; and semiconductor elements formed on the wiring layer and electrically connected to the conductive stripe regions, the semiconductor elements including semiconductor regions with lattice structures identical to those of the conductive stripe regions.

Abstract: Even if undecided portion is contained in the data which is necessary for a series of business processings, necessary data is transmitted to the business processing section which wants to confirm the necessary data without carrying out the destination specifying operation. When inputting data from the business processing section in charge of input, parameters representing the degrees of decision are input together with the data and are stored in a database which is common to the business processing sections, the progress stage of a series of business processings is judged on the basis of a progress stage definition table in which the relation between the input situation of the data items and the parameters, and the progress stages of the series of business processings is defined.

Abstract: A semiconductor memory has bit lines, word lines, ground lines, and memory cells. The bit lines intersect the word and ground lines, to form intersections where the memory cells are arranged, respectively. Each of the memory cells consists of a double-emitter transistor. This transistor has a collector, a first emitter, and a second emitter. Each base-emitter junction of the transistor has an N-shaped negative differential current-voltage characteristic that shows a relatively small gain up to a peak current and a relatively large gain after a valley current. The first emitter of each transistor is connected to a corresponding one of the ground lines. The second emitter is connected to a corresponding one of the word lines. The collector is connected to a corresponding one of the bit lines. Each of the memory cells has a small number of elements and requires only a small area.

Abstract: A semiconductor integrated circuit device including: an off-substrate having a semiconductor surface with a plurality of steps each having a height of one monolayer and extending in one direction; a wiring layer formed on the semiconductor surface of the off-substrate and made of semiconductor material, the wiring layer including a plurality of conductive stripe regions and high resistance strip regions disposed in a stripe pattern, each stripe region extending in a direction parallel with the steps, and the conductive stripe regions and the high resistance stripe regions both having lattice structures identical to those of underlying surfaces; and semiconductor elements formed on the wiring layer and electrically connected to the conductive stripe regions, the semiconductor elements including semiconductor regions with lattice structures identical to those of the conductive stripe regions.

Abstract: A semiconductor device includes a layer 16 of intermetallic compound layer 16 formed on a base substrate 10. The intermetallic compound is a ternary intermetallic compound 16 mixing a set amount of In with one of CoGa, NiGa, FeGa, CoAl, NiAl and FeAl . Twice of a lattice constant of the ternary intermetallic compound 16 is substantially equal to a lattice constant of a compound semiconductor forming the base substrate 10. Accordingly, the layer 16 of the intermetallic compound free from misfit dislocations can be formed on the semiconductor substrate or the semiconductor layer, and semiconductor elements can be formed on the wiring layer of the intermetallic compound layer 16.

Abstract: A semiconductor memory has bit lines, word lines, ground lines, and memory cells. The bit lines intersect the word and ground lines, to form intersections where the memory cells are arranged, respectively. Each of the memory cells consists of a double-emitter resonance-tunnel-hot-electron transistor. This transistor has a collector, a first emitter, and a second emitter. Each base-emitter junction of the transistor has an N-shaped negative differential current-voltage characteristic that shows a relatively small gain up to a peak current and a relatively large gain after a valley current. The transistor has a resonance tunnel barrier and a collector barrier so that most of electrons injected from a first level are reflected by the collector barrier, to provide no collector current, and electrons from a second level or electrons thermally excited pass over the collector barrier, to provide a collector current. The first emitter of each transistor is connected to a corresponding one of the ground lines.

Abstract: A pair of polarizing plates are disposed on two sides of an STN type liquid crystal cell constituted by a liquid crystal twist-aligned at a twist angle of 180.degree. to 270.degree.. A retardation plate is disposed between one of the polarizing plates and the liquid crystal cell in such a manner that the optical axis of the retardation plate crosses the transmission axis of the adjacent polarizing plate at 35.degree. to 55.degree.. The pair of polarizing plates are arranged such that their transmission axes are parallel to each other. The liquid crystal cell is arranged such that the optical axis of the retardation plate crosses the aligning direction of the liquid crystal molecules on the substrate side adjacent to the retardation plate at a predetermined angle. A driving circuit is connected to the liquid crystal cell.

Abstract: A selective growth mask having a plurality of openings is formed on a semiconductor substrate. Desired epitaxially grown regions are formed on the openings by controlling the upward epitaxial growth from the openings. Two resonance tunnel barrier diodes are formed on respective separated two epitaxially grown regions and connected together. Thereafter, a tunnel barrier diode is formed on the connected two resonance tunnel barrier diodes to form a composite functional element having an SRAM function. A number of composite functional elements can be integrally formed on a semiconductor substrate by selective growth and a small number of fine processes.

Abstract: A memory device comprises a row address signal line Ax, a pair of column address signal lines Ay1, Ay2, a standby signal line Sb, a memory cell provided at an area where the row address signal line Ax intersects with the column address signal lines Ay1, Ay2, and a row address signal line driver BD provided on one end of the row address signal line. The row address signal line driver BD comprises a driver transistor BDTr of a double-emitter type, driver transistor BDTr including one collector electrode CBD, and two emitter electrodes of different areas and exhibiting negative differential characteristics. The smaller-area emitter electrode EBD1 is grounded, and the collector electrode CBD is connected to the row address signal line Ax.

Abstract: A hetero-bipolar transistor includes a collector layer of a first conductivity type, a base layer of a second conductivity type provided on the collector layer, a first emitter structure of the first conductivity type provided on the base layer, and a second emitter structure of the first conductivity type and provided on the base layer, wherein the first and second emitter structures are doped with respect to the base layer, with a sufficiently high impurity concentration level such that a Zener breakdown occurs at the p-n junction formed between the base layer and the first or second emitters upon application of a reverse bias voltage.

Abstract: A selective growth mask having a plurality of openings is formed on a semiconductor substrate. Desired epitaxially grown regions are formed on the openings by controlling the upward epitaxial growth from the openings. Two resonance tunnel barrier diodes are formed on respective separated two epitaxially grown regions and connected together. Thereafter, a tunnel barrier diode is formed on the connected two resonance tunnel barrier diodes to form a composite element having an SRAM function. A number of composite functional elements can be integrally formed on a semiconductor substrate by selective growth and a small number of fine processes.

Abstract: A memory device includes a first address signal line, a pair of second address signal lines, a standby signal line, and a memory cell provided at a cross point at which the first address signal line crosses the pair of second address signal lines. The memory cell includes first and second elements connected, via a connection node, in series between the pair of second address signal lines in a forward direction, each of the first and second elements having a negative-differential conductance characteristic. A threshold diode is connected between the first address signal line and the connection node, and has a characteristic in which a current flows in the threshold diode when a voltage applied across the threshold diode exceeds threshold voltages. A gate is connected to the standby signal line and controls currents flowing in the first and second elements.

Abstract: A resilient surface sheet element 14 is vacuum molded from a resilient laminate sheet member 13 including a skin sheet 10 and a foam sheet 12. The resilient surface sheet element 14 is placed in a predetermined recess 16 of a female mold 15 for molding an instrument panel. After a first thermoplastic resin 18 is fed into a space between a male mold 17 and the resilient surface sheet element 14 placed in the female mold 15, the female mold 15 and the male mold 17 are closed tightly. The first thermoplastic resin 18 then flows through a first cavity section formed on a rear face of the resilient surface sheet element 14 to be integrated with the resilient surface sheet element 14. Before the first plastic resin 18 completely hardens in the first cavity section, a second thermoplastic resin 21 is injected from an injection gate 20 into a second cavity section adjacent to the first cavity section to securely fuse and join with the first thermoplastic resin 18.

Abstract: A semiconductor memory device comprises a memory cell transistor that includes two active parts each including therein an emitter and a base and showing a negative differential resistance. The collector layer is shared commonly by the two active parts and is connected to a bit line, while the emitters forming the two active parts are connected to respective word lines that form a word line pair. The bit line and the word lines forming the word line pair are biased to realize a bistable operational state in the memory cell transistor to hold the information.

Abstract: A semiconductor integrated circuit device comprising a negative differential resistance element, such as an RHET and RBT, and a field effect transistor, such as an SBFET and heterojunction type FET, which are formed on the same semiconductor substrate, a base layer of the negative differential resistance element and a channel layer of the field effect transistor being formed on the same epitaxial layer, and the same conductive material is used to simultaneously form an emitter electrode and a gate. A monolithic integration of both the element and transistor can be achieved both rationally and easily.

Abstract: A logic circuit including a transistor having a control electrode connected to three input terminals at which are received three respective input signals, each having, selectively, either a high or a low voltage level, and first and second electrodes, one thereof connected to a first power supply potential and the other thereof connected through a diode having N-type negative differential resistance to a second, lower power supply potential. An output terminal is connected to one of the first and second electrodes of the transistor for deriving an output signal.

Abstract: A quantum semiconductor device comprises a channel region formed with a two-dimensional carrier gas, a Schottky electrode structure provided on the channel region for creating a depletion region in the channel region to extend in a lateral direction such that the two-dimensional carrier gas is divided into a first region and a second region, a quantum point contact formed in the depletion region to connect the first and second regions of the two-dimensional carrier gas in a longitudinal direction, an emitter electrode provided on the channel region in correspondence to the first region of the two-dimensional carrier gas, one or more collector electrodes provided on the channel region in correspondence to the second region of the two-dimensional carrier gas, and another Schottky electrode structure provided in correspondence to the first region for creating a depletion region therein such that a path of the carriers entering into the quantum point contact is controlled asymmetrical with respect to a hypothetic