Patents by Inventor Toshihiko Mori

Toshihiko Mori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5438018
    Abstract: A selective growth mask having a plurality of openings is formed on a semiconductor substrate. Desired epitaxially grown regions are formed on the openings by controlling the upward epitaxial growth from the openings. Two resonance tunnel barrier diodes are formed on respective separated two epitaxially grown regions and connected together. Thereafter, a tunnel barrier diode is formed on the connected two resonance tunnel barrier diodes to form a composite element having an SRAM function. A number of composite functional elements can be integrally formed on a semiconductor substrate by selective growth and a small number of fine processes.
    Type: Grant
    Filed: December 7, 1993
    Date of Patent: August 1, 1995
    Assignee: Fujitsu Limited
    Inventors: Toshihiko Mori, Yoshiki Sakuma
  • Patent number: 5438539
    Abstract: A memory device includes a first address signal line, a pair of second address signal lines, a standby signal line, and a memory cell provided at a cross point at which the first address signal line crosses the pair of second address signal lines. The memory cell includes first and second elements connected, via a connection node, in series between the pair of second address signal lines in a forward direction, each of the first and second elements having a negative-differential conductance characteristic. A threshold diode is connected between the first address signal line and the connection node, and has a characteristic in which a current flows in the threshold diode when a voltage applied across the threshold diode exceeds threshold voltages. A gate is connected to the standby signal line and controls currents flowing in the first and second elements.
    Type: Grant
    Filed: September 2, 1994
    Date of Patent: August 1, 1995
    Assignee: Fujitsu Limited
    Inventor: Toshihiko Mori
  • Patent number: 5429786
    Abstract: A resilient surface sheet element 14 is vacuum molded from a resilient laminate sheet member 13 including a skin sheet 10 and a foam sheet 12. The resilient surface sheet element 14 is placed in a predetermined recess 16 of a female mold 15 for molding an instrument panel. After a first thermoplastic resin 18 is fed into a space between a male mold 17 and the resilient surface sheet element 14 placed in the female mold 15, the female mold 15 and the male mold 17 are closed tightly. The first thermoplastic resin 18 then flows through a first cavity section formed on a rear face of the resilient surface sheet element 14 to be integrated with the resilient surface sheet element 14. Before the first plastic resin 18 completely hardens in the first cavity section, a second thermoplastic resin 21 is injected from an injection gate 20 into a second cavity section adjacent to the first cavity section to securely fuse and join with the first thermoplastic resin 18.
    Type: Grant
    Filed: October 29, 1993
    Date of Patent: July 4, 1995
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Norio Jogan, Tetsuya Fujii, Akiyoshi Nagano, Toshihiko Mori
  • Patent number: 5311465
    Abstract: A semiconductor memory device comprises a memory cell transistor that includes two active parts each including therein an emitter and a base and showing a negative differential resistance. The collector layer is shared commonly by the two active parts and is connected to a bit line, while the emitters forming the two active parts are connected to respective word lines that form a word line pair. The bit line and the word lines forming the word line pair are biased to realize a bistable operational state in the memory cell transistor to hold the information.
    Type: Grant
    Filed: February 22, 1993
    Date of Patent: May 10, 1994
    Assignee: Fujitsu Limited
    Inventors: Toshihiko Mori, Naoki Yokoyama
  • Patent number: 5294566
    Abstract: A semiconductor integrated circuit device comprising a negative differential resistance element, such as an RHET and RBT, and a field effect transistor, such as an SBFET and heterojunction type FET, which are formed on the same semiconductor substrate, a base layer of the negative differential resistance element and a channel layer of the field effect transistor being formed on the same epitaxial layer, and the same conductive material is used to simultaneously form an emitter electrode and a gate. A monolithic integration of both the element and transistor can be achieved both rationally and easily.
    Type: Grant
    Filed: July 21, 1992
    Date of Patent: March 15, 1994
    Assignee: Fujitsu Limited
    Inventor: Toshihiko Mori
  • Patent number: 5281871
    Abstract: A logic circuit including a transistor having a control electrode connected to three input terminals at which are received three respective input signals, each having, selectively, either a high or a low voltage level, and first and second electrodes, one thereof connected to a first power supply potential and the other thereof connected through a diode having N-type negative differential resistance to a second, lower power supply potential. An output terminal is connected to one of the first and second electrodes of the transistor for deriving an output signal.
    Type: Grant
    Filed: November 21, 1991
    Date of Patent: January 25, 1994
    Assignee: Fujitsu Limited
    Inventors: Toshihiko Mori, Motomu Takatsu
  • Patent number: 5280181
    Abstract: A quantum semiconductor device comprises a channel region formed with a two-dimensional carrier gas, a Schottky electrode structure provided on the channel region for creating a depletion region in the channel region to extend in a lateral direction such that the two-dimensional carrier gas is divided into a first region and a second region, a quantum point contact formed in the depletion region to connect the first and second regions of the two-dimensional carrier gas in a longitudinal direction, an emitter electrode provided on the channel region in correspondence to the first region of the two-dimensional carrier gas, one or more collector electrodes provided on the channel region in correspondence to the second region of the two-dimensional carrier gas, and another Schottky electrode structure provided in correspondence to the first region for creating a depletion region therein such that a path of the carriers entering into the quantum point contact is controlled asymmetrical with respect to a hypothetic
    Type: Grant
    Filed: June 3, 1992
    Date of Patent: January 18, 1994
    Assignee: Fujitsu Limited
    Inventors: Miyoshi Saito, Toshihiko Mori
  • Patent number: 5270675
    Abstract: A highly conductive magnetic material useful for a magnet or a magnetic core for an electromagnet, obtained by molding copper or a copper alloy having ferrite dispersed therein.
    Type: Grant
    Filed: April 22, 1991
    Date of Patent: December 14, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshihiko Mori, Hikohiro Togane, Tonizo Minezaki
  • Patent number: 5238628
    Abstract: A shaped product having a shape corresponding to a flare-like deflection yoke core is formed from clay as a raw material of ferrite by a wet molding method; parting grooves are formed in the inner or outer circumferential surface of the shape product while it is green; and the thus obtained shaped product is dried and calcined, whereby a deflection yoke core is produced.
    Type: Grant
    Filed: April 9, 1992
    Date of Patent: August 24, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshihiko Mori, Takaichi Suzuki
  • Patent number: 5162877
    Abstract: A semiconductor integrated circuit device comprising a negative differential resistance element, such as an RHET and RBT, and a field effect transistor, such as an SBFET and heterojunction type FET, which are formed on the same semiconductor substrate, a base layer of the negative differential resistance element and a channel layer of the field effect transistor being formed on the same epitaxial layer, and the same conductive material is used to simultaneously form an emitter electrode and a gate. A monolithic integration of both the element and transistor can be achieved both rationally and easily.
    Type: Grant
    Filed: April 30, 1991
    Date of Patent: November 10, 1992
    Assignee: Fujitsu Limited
    Inventor: Toshihiko Mori
  • Patent number: 5153539
    Abstract: A magnetic core for a signal line filter adapted to be assembled in a terminal connector for a signal line cable for connecting electronic devices to form a signal line filter, wherein the magnetic core is provided with pin insertion holes each having a tapered portion in the direction of thickness of the magnetic core, or tapered portions at both sides in the direction of thickness of the magnetic core.
    Type: Grant
    Filed: September 19, 1991
    Date of Patent: October 6, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hideo Hara, Hikohiro Togane, Toshihiko Mori
  • Patent number: 5129858
    Abstract: An air-conditioning grille comprises an inner case having an opening through which the wind blows out located in a wind blowing duct. In the duct, provided are plural wind deflecting plates which are bendable so as to make both the ends thereof extend substantially crossing the blowing direction. In the duct provided is a connecting member which connects the upstream ends of the wind deflecting plates together and restricts rotations of these connecting portions relative to each other. Also provided is an operation member to be operated to bend the wind deflecting plates. One transfer shaft is provided to transfer an operational force of the operation member, at the time of its operation, to the connecting member. In order to prevent the connecting member from rotating itself about the transfer shaft with operation of the operation member, rotation moments of the connecting member about the transfer shaft substantially cancel one another.
    Type: Grant
    Filed: August 16, 1990
    Date of Patent: July 14, 1992
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Takahiro Komori, Kazuo Fujihara, Hiroshi Iwata, Toshihiko Mori
  • Patent number: 5128090
    Abstract: A vacuum forming process, and an apparatus for carrying out the same, for imparting a predetermined shape to a sheet material. The process includes the steps of placing a thermally softened sheet material onto a molding surface of a mold and evacuating air remaining between the molding surface of the mold and the sheet material, thereby bringing the sheet material into a close contact with the molding surface of the surface of the mold. The vacuum forming process and apparatus is adapted for giving a predetermined shape to a sheet material having a low elongation ratio.
    Type: Grant
    Filed: December 10, 1990
    Date of Patent: July 7, 1992
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Tetsuya Fujii, Toru Kai, Akiyoshi Nagano, Toshihiko Mori
  • Patent number: 5023836
    Abstract: A semiconductor memory device comprises a transistor and a resistor. The transistor has negative differential resistance characteristics in an emitter current or a source current thereof. Therefore the semiconductor memory device has few elements and a simplified configuration, and thus high speed operation and large scale integration can be realized. Further, in the semiconductor memory device of the present invention, several variations in design are possible.
    Type: Grant
    Filed: July 18, 1989
    Date of Patent: June 11, 1991
    Assignee: Fujitsu Limited
    Inventor: Toshihiko Mori
  • Patent number: 5019185
    Abstract: A high strength Cu-Ni-Sn alloy, comprising 3-25% Ni, 3-9% Sn, 0.05-1.5% Mn, balance Cu, is heated to a temperature of 800.degree. C. or above in a single-phase region. This heat treatment is followed by quenching and subsequent heating at a temperature range of 600.degree.-770.degree. C. in a two-phase region, followed by quenching and a finishing process with a ratio of 0-60%. Thereafter, the processed alloy is subjected to a final heat-treatment at a temperature of 350.degree.-500.degree. C.
    Type: Grant
    Filed: November 15, 1989
    Date of Patent: May 28, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takashi Nakajima, Kenji Kubozono, Toshihiko Mori, Takefumi Ito, Kimio Hashitsume, Shinichi Iwase
  • Patent number: 4999674
    Abstract: There is an image forming apparatus in which images of a plurality of originals set on the original plate glass are individually exposed, scanned and read, and the read images are synthesized and recorded at arbitrary positions on a recording paper. This apparatus also has a device to record the images on the front and back surfaces of the recording paper. The synthetic recording and the front and back surface recording can be arbitrarily switched and selected. This apparatus is provided with a trimming function to erase unnecessary image portions of the images, a masking function to prevent the shaded portions from being recorded on an paper, and the image shift function to adjust the synthesizing positions of the images on the recording paper for every image.
    Type: Grant
    Filed: February 27, 1989
    Date of Patent: March 12, 1991
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masanori Miyata, Yutaka Komiya, Shinichi Nakamura, Masayuki Hirose, Toshihiko Mori, Tomobumi Nakayama
  • Patent number: 4970569
    Abstract: A nickel based material for a semiconductor apparatus is provided which includes between 0.5 and 5% of at least one material selected from the group consisting of cobalt, iron, aluminum, manganese, silicon, carbon, and copper; residual nickel; and unavoidable impurties. With this nickel based material, electrical conductivity thereof can be maintained within a proper value and the plate film adhesion in silver plating nickel based products can be improved remarkably and both heat dissipation capacity and the coefficient of thermal expansion can be improved.
    Type: Grant
    Filed: May 1, 1989
    Date of Patent: November 13, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshihiko Mori, Kenji Kubosono
  • Patent number: 4941149
    Abstract: A method for melting and/or refining metals and a cooling device for the graphite electrode used for the same are disclosed. Melting and/or refining of metal such as steel-making are performed in an electric arc furnace by energizing three graphite electrode sets each corresponding to each phase of a three-phase AC power source and consisting of a vertical succession of graphite electrodes as typically shown at 10 in FIGS. 2, 3 and 4, connected to one another via nipples.During the melting and/or refining of metal, a cooling liquid 11, substantially consisting of water for instance, is continuously blown against the outer periphery 10a of at least one of each set of graphite electrodes, specifically a graphite electrode 10 extending between an electrode holder and a furnace top cover. The liquid coolant 11 is jet not in the horizontal direction but in a downwardly or upwardly inclined direction at an angle of 10.degree. to 35.degree. C. with respect to the horizontal.
    Type: Grant
    Filed: August 15, 1988
    Date of Patent: July 10, 1990
    Assignee: Nippon Carbon Co., Ltd.
    Inventors: Yakka Nakamoto, Toshihiko Mori
  • Patent number: 4907196
    Abstract: A semiconductor memory device comprises a transistor having such a current characteristic that a base current has a differential negative resistance characteristic and a collector current greatly flows after the differential negative resistance characteristic occurs in the base current when a base-emitter voltage is increased, a load coupled in series between a collector and a base of the transistor, first and second input terminals coupled to the base of the transistor through a base resistance of the transistor, and an ouptut terminal coupled to the collector of the transistor.
    Type: Grant
    Filed: April 21, 1988
    Date of Patent: March 6, 1990
    Assignee: Fujitsu Limited
    Inventors: Toshihiko Mori, Toshiro Futatsugi
  • Patent number: 4849934
    Abstract: A logic circuit including a resonant-tunneling transistor having a superlattice containing at least one quantum well layer, and a constant current source operatively connected between a base and an emitter of the transistor and supplying a constant current to said base. The transistor has a differential negative-resistance characteristic with at least one resonant point in a relationship between a current flowing in the base and a voltage between the base and emitter, and having at least two stable base current values at both sides of the resonant point on the characteristic, defined by the changeable base.multidot.emitter voltage. By supplying the base.multidot.emitter voltage having an amplitude of at least two amplitudes corresponding to the stable base current values, the transistor holds data corresponding to the base.multidot.emitter voltage.
    Type: Grant
    Filed: October 10, 1986
    Date of Patent: July 18, 1989
    Assignee: Fujitsu Limited
    Inventors: Naoki Yokoyama, Toshihiko Mori