Patents by Inventor Toshihiro Yamashita

Toshihiro Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6783640
    Abstract: In a sputtering method for forming a film on a substrate in a film forming space while monitoring emission intensity of plasma, the method comprises the steps of detecting a thickness of the film formed on the substrate; comparing a detected value with a preset value of the film thickness; and deciding a target value of the emission intensity in accordance with a compared result. With the method, a transparent conductive film is formed which has high uniformity in film thickness, sheet resistance and transmittance and hence has superior characteristics.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: August 31, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toshihiro Yamashita, Hiroshi Echizen, Yasuyoshi Takai, Hidetoshi Tsuzuki
  • Patent number: 6740210
    Abstract: Since the transfer speed of a substrate is controlled to compensate for a film-forming rate, and an electric power applied to heating means for heating the substrate is controlled so that thermal equilibrium of the substrate is maintained, a film having a uniform thickness and quality can be stably formed even when sputtering is performed for a long time.
    Type: Grant
    Filed: October 11, 2001
    Date of Patent: May 25, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroshi Echizen, Toshihiro Yamashita
  • Patent number: 6716324
    Abstract: Provided is a method of forming a transparent, conductive film on a semiconductor layer formed on a substrate, by sputtering, wherein voltages are applied independently of each other to both a target and the substrate, respectively, and a bias voltage appearing in the substrate is controlled so as to form the transparent, conductive film on only a portion except for a defective region of the semiconductor layer, thereby restraining shunting of the transparent, conductive film and achieving excellent appearance thereof. Also provided are a defective region compensation method of a semiconductor layer, a photovoltaic element, and a method of producing the photovoltaic element.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: April 6, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toshihiro Yamashita, Yasuyoshi Takai, Hiroshi Izawa
  • Patent number: 6677171
    Abstract: A collective substrate of active-matrix substrates is divided into a first block and a second block. In cells of the first block and the second block, from a corresponding signal input pad group, an inspection scanning signal is inputted via a scanning-line short ring connecting line to scanning lines, an inspection display signal is inputted via a signal-line short ring connecting line to signal lines, and an auxiliary capacity wire signal is inputted via an auxiliary capacity wire main wire connecting line to auxiliary capacity wires. This arrangement makes it possible to perform an electrical inspection with high accuracy and efficiency on a large-format active-matrix substrate, and to manufacture an inspection probe frame in a simple manner at low cost.
    Type: Grant
    Filed: November 14, 2000
    Date of Patent: January 13, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hisashi Nagata, Mikio Katayama, Toshihiro Yamashita, Manabu Takahama
  • Patent number: 6648128
    Abstract: A conveyor is provided that is capable of preventing degradation in quality of an article being conveyed. The conveyor includes a conveyor belt; and a rolling element rotatably provided at a surface of the conveyor belt. A plurality of rolling elements are provided along a conveying direction. The conveyor further includes a holder provided at the surface of the conveyor belt, for rotatably holding the corresponding rolling element. The rolling element has a ball shape.
    Type: Grant
    Filed: April 29, 2002
    Date of Patent: November 18, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshihiro Yamashita, Toshio Komemura, Toshihiko Noguchi
  • Publication number: 20030153165
    Abstract: The method of the present invention is a method of forming a silicon-based semiconductor layer by introducing a source gas into a vacuum vessel and forming a silicon-based semiconductor layer containing a microcrystal on a substrate introduced into the vacuum vessel by plasma CVD, which comprises a first step of forming a first region with a source gas containing halogen atoms, and a second step of forming a second region on the first region under a condition where the source gas containing halogen atoms in the second step is lower in gas concentration than that of the first step, thereby providing a method of forming a silicon-based semiconductor layer having an excellent photoelectric characteristic at a film forming rate of an industrially practical level and a photovoltaic element using the silicon-based semiconductor layer formed by the method.
    Type: Application
    Filed: October 24, 2001
    Publication date: August 14, 2003
    Inventors: Takaharu Kondo, Masafumi Sano, Akira Sakai, Yasuyoshi Takai, Ryo Hayashi, Toshihiro Yamashita
  • Publication number: 20030042115
    Abstract: A conveyor is provided that is capable of preventing degradation in quality of an article being conveyed. The conveyor includes a conveyor belt; and a rolling element rotatably provided at a surface of the conveyor belt. A plurality of rolling elements are provided along a conveying direction. The conveyor further includes a holder provided at the surface of the conveyor belt, for rotatably holding the corresponding rolling element. The rolling element has a ball shape.
    Type: Application
    Filed: April 29, 2002
    Publication date: March 6, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshihiro Yamashita, Toshio Komemura, Toshihiko Noguchi
  • Publication number: 20020144726
    Abstract: Provided is a method of forming a transparent, conductive film on a semiconductor layer formed on a substrate, by sputtering, wherein voltages are applied independently of each other to both a target and the substrate, respectively, and a bias voltage appearing in the substrate is controlled so as to form the transparent, conductive film on only a portion except for a defective region of the semiconductor layer, thereby restraining shunting of the transparent, conductive film and achieving excellent appearance thereof. Also provided are a defective region compensation method of a semiconductor layer, a photovoltaic element, and a method of producing the photovoltaic element.
    Type: Application
    Filed: January 30, 2002
    Publication date: October 10, 2002
    Inventors: Toshihiro Yamashita, Yasuyoshi Takai, Hiroshi Izawa
  • Publication number: 20020134670
    Abstract: In a sputtering method for forming a film on a substrate in a film forming space while monitoring emission intensity of plasma, the method comprises the steps of detecting a thickness of the film formed on the substrate; comparing a detected value with a preset value of the film thickness; and deciding a target value of the emission intensity in accordance with a compared result. With the method, a transparent conductive film is formed which has high uniformity in film thickness, sheet resistance and transmittance and hence has superior characteristics.
    Type: Application
    Filed: January 18, 2002
    Publication date: September 26, 2002
    Inventors: Hiroshi Echizen, Yasuyoshi Takai, Hidetoshi Tsuzuki, Toshihiro Yamashita
  • Publication number: 20020086546
    Abstract: A plasma processing system comprises a processing chamber into and from which processing gas is inlet and outlet; a pair of electrodes disposed so as to mutually oppose within the processing chamber; a RF feeding apparatus for generating plasma between the pair of electrodes; a retaining/removal apparatus for retaining a substrate to be processed on and removal from a sample table while one of the pair of electrodes is taken as the sample table; and a detection apparatus for detecting the electrostatic-chucking state of the substrate and for detecting removal state of electrical charges from the substrate, on the basis of variations in impedance arising between the sample table and the substrate.
    Type: Application
    Filed: July 10, 2001
    Publication date: July 4, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshihiro Yamashita, Hirotoshi Ise
  • Publication number: 20020046943
    Abstract: Since the transfer speed of a substrate is controlled to compensate for a film-forming rate, and an electric power applied to heating means for heating the substrate is controlled so that thermal equilibrium of the substrate is maintained, a film having a uniform thickness and quality can be stably formed even when sputtering is performed for a long time.
    Type: Application
    Filed: October 11, 2001
    Publication date: April 25, 2002
    Inventors: Hiroshi Echizen, Toshihiro Yamashita
  • Patent number: 6297520
    Abstract: In an active matrix substrate having thereon a matrix of pixels each composed of a pair of a TFT and a pixel electrode, when the shorting of the pixel electrodes in adjacent pixels occurs, an electrical connection between the pixel electrode and drain electrode in the TFT of a matching pair in either of the shorted pixel electrodes is cut. For example, when the shorting of two adjacent pixels occurs, the pixel electrodes in both the pixels are driven by the TFT in the non-cut pixel. This arrangement makes it possible to make a display defect resulted from the shorting of adjacent pixels on the active matrix substrate less noticeable, and hence to upgrade display quality.
    Type: Grant
    Filed: August 20, 1999
    Date of Patent: October 2, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masumi Kubo, Toshihiro Yamashita, Yoshimitsu Tajima
  • Patent number: 6172410
    Abstract: A collective substrate of active-matrix substrates is divided into a first block and a second block. In cells of the first block and the second block, from a corresponding signal input pad group, an inspection scanning signal is inputted via a scanning-line short ring connecting line to scanning lines, an inspection display signal is inputted via a signal-line short ring connecting line to signal lines, and an auxiliary capacity wire signal is inputted via an auxiliary capacity wire main wire connecting line to auxiliary capacity wires. This arrangement makes it possible to perform an electrical inspection with high accuracy and efficiency on a large-format active-matrix substrate, and to manufacture an inspection probe frame in a simple manner at low cost.
    Type: Grant
    Filed: July 6, 1999
    Date of Patent: January 9, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hisashi Nagata, Mikio Katayama, Toshihiro Yamashita, Manabu Takahama
  • Patent number: 6081250
    Abstract: To enhance the display quality by improving the writing characteristic of active matrix display device.A plurality of signal lines of video signals are provided for pixels of each column arranged in two-dimensional array, and the driving element of each pixel is designed to be driven by any one of the signal lines, so that the scanning time of each line may be extended longer than one horizontal scanning period.
    Type: Grant
    Filed: June 27, 1994
    Date of Patent: June 27, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takayuki Shimada, Toshihiro Yamashita, Yutaka Takafuji
  • Patent number: 6028580
    Abstract: A driving circuit integrated type active-matrix liquid crystal display device is arranged such that a buffer composed of a P-channel thin film transistor and an N-channel thin film transistor that are connected in series is adopted for the P-channel thin film transistor and an N-channel thin film transistor; at least one of the P-channel thin film transistor and the N-channel thin film transistor is composed of a plurality of thin film transistors that are connected in parallel; and at least one of a power source line and an output line connected to the plurality of thin film transistors connected in parallel is formed in a wiring pattern composed of a main wiring section and a branched wiring section branched into respective thin film transistors. The described arrangement permits a line-shaped defect due to a defective thin film transistor which constitutes a buffer of the drive circuit to be eliminated with ease, while improving a yield of panels.
    Type: Grant
    Filed: September 25, 1996
    Date of Patent: February 22, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Seishi Kosegawa, Toshihiro Yamashita, Yutaka Takafuji
  • Patent number: 5977563
    Abstract: In an active matrix substrate having thereon a matrix of pixels each composed of a pair of a TFT and a pixel electrode, when the shorting of the pixel electrodes in adjacent pixels occurs, an electrical connection between the pixel electrode and drain electrode in the TFT of a matching pair in either of the shorted pixel electrodes is cut. For example, when the shorting of two adjacent pixels occurs, the pixel electrodes in both the pixels are driven by the TFT in the non-cut pixel. This arrangement makes it possible to make a display defect resulted from the shorting of adjacent pixels on the active matrix substrate less noticeable, and hence to upgrade display quality.
    Type: Grant
    Filed: April 15, 1997
    Date of Patent: November 2, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masumi Kubo, Toshihiro Yamashita, Yoshimitsu Tajima
  • Patent number: 5825342
    Abstract: A liquid crystal display, employed in a projector, including a liquid crystal panel using, for example, a TN liquid crystal, having visual angle characteristics that the direction of a visual angle in which the contrast reaches its maximum does not match with the direction of the normal line, and transmitting incident light from an opposing substrate side while modulating the same. The liquid crystal panel can reverse the sides and the top and bottom of an image by reversing the orders of image signal application to the signal lines and scanning signal application to the scanning lines, respectively. Signal input units are formed at two opposing ends of the liquid crystal panel and a mounting means for mounting the liquid crystal display to the projector is formed point symmetry with respect to the center of the liquid crystal panel.
    Type: Grant
    Filed: July 13, 1995
    Date of Patent: October 20, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasunobu Akebi, Masumi Kubo, Toshihiro Yamashita
  • Patent number: 5801673
    Abstract: A liquid crystal display device which includes: a plurality of source bus lines in parallel with each other; a plurality of gate bus lines in parallel with each other, crossing the source bus lines; a switching element connected to one of the plurality of source bus lines and one of the gate bus lines; a pixel portion connected to the switching element; and a source drive circuit for supplying a data signal to the plurality of source bus lines, wherein the source drive circuit has a data signal line connected to the respective source bus lines, and the data signal line forms a closed circuit, thereby making a delay time of the data signal supplied to the plurality of source bus lines uniform is disclosed.
    Type: Grant
    Filed: August 29, 1994
    Date of Patent: September 1, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takayuki Shimada, Toshihiro Yamashita, Yutaka Takafuji, Toshio Matsumoto
  • Patent number: 5798742
    Abstract: An active matrix panel includes: a liquid crystal section having a plurality of pixels arranged in a matrix; a plurality of source lines for applying video signals to the plurality of pixels; a source driver for sequentially applying the video signals to the plurality of source lines; and a plurality of sample hold capacitances for holding the video signals applied to the source line, wherein each of the source lines is connected to a predetermined number of the sample hold capacitances in parallel.
    Type: Grant
    Filed: December 16, 1994
    Date of Patent: August 25, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahide Watatani, Toshihiro Yamashita, Takayuki Shimada
  • Patent number: 5744820
    Abstract: With respect to at least one of a plurality of TFTs constituting a liquid crystal display device; a signal wiring having one end functioning as a gate electrode of the TFT is formed so as to include: a main portion, formed by patterning a first wiring layer, having a disconnected portion in the vicinity of an active region of the transistor; and a connecting portion, formed by patterning a second wiring layer which is different from the first wiring layer, for interconnecting the disconnected portion. Thus, the breakdown of the gate insulating film of the TFTs during the ion implantation process can be prevented.
    Type: Grant
    Filed: May 15, 1995
    Date of Patent: April 28, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasuhiro Matsushima, Toshihiro Yamashita, Takayuki Shimada