Patents by Inventor Toshihiro Yamashita

Toshihiro Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5701165
    Abstract: A projection-type liquid crystal display is provided with an image-outputting section which includes a liquid-crystal panel. On the light-releasing side of the liquid crystal panel, an active-matrix substrate and a polarizing element are bonded to each other with a bonding material that has virtually the same refractive index as that of these members so as to reduce internal reflection on the light-releasing surface of the active-matrix substrate and external reflection on the light-incident surface of the polarizing element. Further, a reflection-reducing coating layer is formed on the light-releasing surface of the light-releasing-side polarizing element to reduce internal reflection on the light-releasing surface of the polarizing element.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: December 23, 1997
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masumi Kubo, Yasunobu Akebi, Toshihiro Yamashita
  • Patent number: 5659375
    Abstract: A liquid crystal display panel of the invention includes an active matrix substrate. The active matrix substrate includes: a substrate; a plurality of pixel electrodes for driving a liquid crystal, the pixel electrodes being arranged in rows and columns on the substrate; a plurality of data signal lines for supplying data signals to pixel electrodes of a corresponding column; a plurality of switching devices for electrically connecting each data signal line to the pixel electrodes of the corresponding column; a plurality of scanning signal lines for controlling the switching devices to be conductive; and a plurality of storage capacitances respectively connected to terminals of the switching devices which are connected to the pixel electrodes.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: August 19, 1997
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshihiro Yamashita, Masumi Kubo
  • Patent number: 5576730
    Abstract: An active matrix substrate including an external signal supplying circuit for externally supplying the video signals to the data lines. The external signal supplying circuit includes a data line connection section connected to the data lines; an inspection signal inputting section and an inspection signal outputting section both connected to the data line connection section; and a switching device for electrically connecting the inspection signal inputting section or the inspection signal outputting section to the data line connection section.
    Type: Grant
    Filed: April 6, 1993
    Date of Patent: November 19, 1996
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takayuki Shimada, Toshihiro Yamashita, Yutaka Takafuji
  • Patent number: 5528056
    Abstract: A thin-film semiconductor device having a CMOS inverter comprising a pair of n-type and p-type thin-film transistors, wherein the gate electrode of at least one of the paired thin-film transistors comprises a plurality of gate electrode sections spaced apart along the channel length. The channel region of the n-type thin-film transistor is doped with p-type impurities. This structure serves to reduce the leakage current and maintain high OFF resistance for a high source-drain voltage. Further, since a good symmetry of characteristics is maintained between the n-type and p-type thin-film transistors that constitute the CMOS inverter, no appreciable bias is caused in the output voltage of the CMOS inverter.
    Type: Grant
    Filed: February 22, 1995
    Date of Patent: June 18, 1996
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takayuki Shimada, Toshihiro Yamashita, Yasuhiro Matsushima, Yoji Yoshimura, Yutaka Takafuji
  • Patent number: 5506598
    Abstract: An active matrix substrate including a plurality of pixels arranged in a matrix manner and a plurality of switching elements connected in series to each of the plurality of pixels, each of the plurality of switching elements having a gate electrode, a gate electrode of at least one of the plurality of switching elements being electrically isolated from those of the other remaining switching elements.
    Type: Grant
    Filed: January 19, 1993
    Date of Patent: April 9, 1996
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takayuki Shimada, Toshihiro Yamashita, Yutaka Takafuji
  • Patent number: 5506516
    Abstract: In a method of inspecting an active matrix substrate of the invention, the active matrix substrate includes a pixel portion having a plurality of pixels arranged in a matrix, a plurality of scanning lines and data lines for driving the pixel portion, and a drive circuit having one and more video lines, one end of each of the plurality of data lines being connected to one of the video lines. The method of the invention includes the steps of: providing one or more inspecting lines, the other end of each of the plurality of data lines being connected to one of the inspecting lines; applying an inspecting signal to each of the inspecting lines, with the drive circuit being in operation; and inspecting the drive circuit and the plurality of data lines, based on at least one of the signals output from the or each of the video lines in accordance with the inspecting signals.
    Type: Grant
    Filed: September 6, 1994
    Date of Patent: April 9, 1996
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshihiro Yamashita, Yasuhiro Matsushima, Takayuki Shimada, Yutaka Takafuji
  • Patent number: 5453135
    Abstract: A photoelectric conversion device comprising at least a metal layer, a transparent conductive layer disposed on said metal layer, and an active semiconductor layer disposed on said transparent conductive layer, characterized in that said transparent conductive layer comprises a layer having an uneven surface which is composed of a zinc oxide material having an X-ray diffraction pattern in which (a) the peak intensity of the (2,0,0) planes of ZnO.sub.2 is 1/200 or less of (b) the peak intensity of the (0,0,2) planes of ZnO and (c) the peak intensity of the (1,0,1) planes of Zn is 1/200 or less of the peak intensity (b).
    Type: Grant
    Filed: December 28, 1993
    Date of Patent: September 26, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventors: Katsumi Nakagawa, Noboru Toyama, Toshihiro Yamashita
  • Patent number: 5400050
    Abstract: A driving circuit for use in a display apparatus for transmitting a video signal to data lines includes a plurality of shift registers; a control signal generating circuit for outputting a control signal which is at the ON level during a period shorter than a pulse width of signals outputted by the shift registers; a switching circuit controlled to be ON or OFF based on the control signal; and a sampling capacitor for holding the video signal sampled by the switching circuit. In such a driving circuit, the plurality of shift registers sequentially output signals so that the periods in which the signals are high are partially overlapped sequentially. The control signal generating circuit outputs a control signal which is at the On level during a period shorter than the signals from the shift registers. Since the switching circuit is controlled to be ON or OFF based on the control signal, a period in which the switching circuit is conductive is short.
    Type: Grant
    Filed: November 23, 1993
    Date of Patent: March 21, 1995
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshio Matsumoto, Osamu Sasaki, Yasunobu Akebi, Toshihiro Yamashita
  • Patent number: 5279681
    Abstract: A photovoltaic device having a semiconductor body with a pin junction, with reduced time-dependent deterioration, high reliability and a high photoelectric conversion efficiency is disclosed.An i-type semiconductor layer constituting the semiconductor body is composed of a layer having a region containing germanium and at least one region not containing germanium. The at least one region not containing germanium is provided at least at the side of a p-semiconductor layer. The maximum composition ratio of germanium in the region containing amorphous silicon and germanium is within a range from 20 to 70 at.
    Type: Grant
    Filed: February 20, 1992
    Date of Patent: January 18, 1994
    Assignee: Canon Kabushiki Kaisha
    Inventors: Koichi Matsuda, Tsutomu Murakami, Jinsho Matsuyama, Naoto Okada, Toshihiro Yamashita
  • Patent number: 5279679
    Abstract: A multi-layered photovoltaic element obtained by stacking at least three cells for photovoltaic generation. A second cell formed adjacent to a light incident-side cell and adapted to receive light which has passed through the light incident-side cell includes an i-type semiconductor layer having a band gap falling within a range of 1.45 eV to 1.60 eV. The i-type semiconductor layer consists essentially of a silicon-germanium-containing amorphous material.
    Type: Grant
    Filed: February 21, 1992
    Date of Patent: January 18, 1994
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tsutomu Murakami, Jinsho Matsuyama, Koichi Matsuda, Hiroshi Yamamoto, Toshihiro Yamashita
  • Patent number: 5252142
    Abstract: A pin junction photovoltaic element having an i-type semiconductor layer formed of a variable band gap semiconductor material, said i-type semiconductor layer being positioned between a p-type semiconductor layer having a band gap wider than that of said i-type semiconductor layer and an n-type semiconductor layer having a band gap wider than that of said i-type semiconductor layer, characterized in that said i-type semiconductor layer contains a first region (a) which is positioned on the side of said p-type semiconductor layer and also has a graded band gap, a second region (b) which is adjacent to said first region (a) and has a graded band gap, and a third region (c) which is positioned on the side of said n-type semiconductor layer and also has a graded band gap; said i-type semiconductor layer having a minimum band gap at the boundary between said first region (a) and said second region (b); the thickness of said first region (a) being less than one-half of the total thickness of said i-type semiconduct
    Type: Grant
    Filed: November 22, 1991
    Date of Patent: October 12, 1993
    Assignee: Canon Kabushiki Kaisha
    Inventors: Jinsho Matsuyama, Tsutomu Murakami, Koichi Matsuda, Hiroshi Yamamoto, Toshihiro Yamashita
  • Patent number: 4996291
    Abstract: A thermo-shrinkable polyester film of this invention is obtained from a composition that comprises acid components including terephthalic acid and glycol components including ethyleneglycol. The polyester film has a heat-shrinkage ratio of 30% or more in a certain direction at 100.degree. C., and a shrinkage ratio of 5% or more at the point of intersection of a curve showing the internal shrinkage stress of the film and a curve showing the tensile stress of the film.
    Type: Grant
    Filed: September 8, 1989
    Date of Patent: February 26, 1991
    Assignee: Toyo Boseki Kabushiki Kaisha
    Inventors: Yasuo Yoshinaka, Katsuaki Kuze, Tsutomu Isaka, Toshihiro Yamashita, Yujiro Matsuyama, Koichiro Nakamura, Tsuyoshi Matsunaga, Osamu Makimura
  • Patent number: 4963418
    Abstract: A thermo-shrinkable polyester type film having the following shrinking properties:a shrinking ratio in one axis is not less than 30% at 80.degree. C. and not less than 50% at 100.degree. C., anda shrinking ratio in a perpendicular axis to the former axis shows the minimum value at a temperature range of 80.degree..+-.25.degree. C., and the process therefor.This film shows an excellent shrinking properties for packaging.
    Type: Grant
    Filed: January 26, 1989
    Date of Patent: October 16, 1990
    Assignee: Toyo Boseki Kabushiki Kaisha
    Inventors: Tsutomu Isaka, Toshihiro Yamashita